| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 67738
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llvm-svn: 67737
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llvm-svn: 67736
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llvm-svn: 67729
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%a = ...
%b = and i32 %a, 2
%c = srl i32 %b, 1
%d = br i32 %c,
into
%a = ...
%b = and %a, 2
%c = X86ISD::CMP %b, 0
%d = X86ISD::BRCOND %c ...
This applies only when the AND constant value has one bit set and the SRL
constant is equal to the log2 of the AND constant. The back-end is smart enough
to convert the result into a TEST/JMP sequence.
llvm-svn: 67728
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llvm-svn: 67727
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called from llc, not opt, but it's an IR level
optimization nevertheless.)
llvm-svn: 67724
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analysis values, related to the instructions in the basic block.
llvm-svn: 67719
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register classes. Before, MVT::Other would be returned anytime a reg was
in multiple register classes. Now, MVT::Other is only returned if the types
for those register classes differ.
llvm-svn: 67714
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llvm-svn: 67702
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Also fixes SDISel so it *does not* force promote return value if the function is not marked signext / zeroext.
llvm-svn: 67701
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llvm-svn: 67694
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stoppoint nodes around until Legalize; doing this
imposed an ordering on a sequence of loads that
came from different lines, interfering with scheduling.
llvm-svn: 67692
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llvm-svn: 67691
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llvm-svn: 67689
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llvm-svn: 67688
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call, we should treat "i64 zext" as the start of a constant expr, but
"i64 0 zext" as an argument with an obsolete attribute on it (this form
is already tested by test/Assembler/2007-07-30-AutoUpgradeZextSext.ll).
Make the autoupgrade logic more discerning to avoid treating "i64 zext"
as an old-style attribute, causing us to reject a valid constant expr.
This fixes PR3876.
llvm-svn: 67682
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llvm-svn: 67681
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llvm-svn: 67675
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default to verbose.
llvm-svn: 67669
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default to verbose.
llvm-svn: 67668
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llvm-svn: 67667
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not going to persue this further at this time.
llvm-svn: 67666
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precise than it used to be.
llvm-svn: 67662
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llvm-svn: 67661
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llvm-svn: 67658
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llvm-svn: 67657
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llvm-svn: 67656
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autoconf directory, but these paths need to be relative to the main
source directory.
llvm-svn: 67655
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llvm-svn: 67654
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llvm-svn: 67652
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The configure line had --disable-bootstrap, but it was not
clear that this is essential.
llvm-svn: 67651
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llvm-svn: 67649
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llvm-svn: 67647
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llvm-svn: 67642
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to/from integer types that are not intptr_t to convert to intptr_t
then do an integer conversion to the dest type. This exposes the
cast to the optimizer.
llvm-svn: 67638
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and streamline code here a bit.
llvm-svn: 67636
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1. Make instcombine always canonicalize trunc x to i1 into an icmp(x&1). This
exposes the AND to other instcombine xforms and is more of what the code
generator expects.
2. Rewrite the remaining trunc pattern match to use 'match', which
simplifies it a lot.
llvm-svn: 67635
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llvm-svn: 67629
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llvm-svn: 67622
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the target constraint specifies a specific physreg.
llvm-svn: 67618
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llvm-svn: 67617
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fail.
llvm-svn: 67616
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to be returned in DL. LLVM's multiple-return-value support is
not ABI-conforming; front-ends that wish to have code emitted
that conforms to an ABI are currently expected to make
arrangements for this on their own rather than assuming that
multiple-return-values will automatically do the right thing.
This commit doesn't fundamentally change this situation.
llvm-svn: 67588
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canClobberPhysRegDefs if the successor node doesn't
clobber any physical registers.
llvm-svn: 67587
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help out the register pressure reduction heuristics in the case of
nodes with multiple uses. Currently this uses very conservative
heuristics, so it doesn't have a broad impact, but in cases where it
does help it can make a big difference.
llvm-svn: 67586
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llvm-svn: 67580
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llvm-svn: 67578
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the super-register is in the register class we are trying to allocate. Then add the weight to all sub-registers of the super-register even if they are not aliases.
e.g. allocating for GR32, bh is not used, updating bl spill weight.
bl should get the same spill weight otherwise it will be choosen
as a spill candidate since spilling bh doesn't make ebx available.
This fix PR2866.
llvm-svn: 67574
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llvm-svn: 67565
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