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* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-0310-60/+0
| | | | | | These exception-related opcodes are not used any longer. llvm-svn: 185596
* Simplify landing pad lowering.Jakob Stoklund Olesen2013-07-033-26/+26
| | | | | | | | | | | | | | | | | | | | | Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering landing pad arguments. These nodes were previously legalized into CopyFromReg nodes, but that never worked properly because the CopyFromReg node weren't guaranteed to be scheduled at the top of the basic block. This meant the exception pointer and selector registers could be clobbered before being copied to a virtual register. This patch copies the two physical registers to virtual registers at the beginning of the basic block, and lowers the landingpad instruction directly to two CopyFromReg nodes reading the *virtual* registers. This is safe because virtual registers don't get clobbered. A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION nodes. llvm-svn: 185595
* Add MachineBasicBlock::addLiveIn().Jakob Stoklund Olesen2013-07-032-0/+38
| | | | | | | This function adds a live-in physical register to an MBB and ensures that it is copied to a virtual register immediately. llvm-svn: 185594
* Have ARMBaseRegisterInfo::getCallPreservedMask return the 'correct' mask for ↵Stephen Lin2013-07-032-10/+13
| | | | | | | | the GHC calling convention. This is purely academic because GHC calls are always tail calls so the register mask will never be used; however, this change makes the code clearer and brings the ARM implementation of the GHC calling convention in line with the X86 implementation. Also, it might save someone else some time trying to figuring out what is happening... llvm-svn: 185592
* Hoist all of the Entry.getLoc() calls int a single variable.Eric Christopher2013-07-031-7/+8
| | | | llvm-svn: 185589
* Make DotDebugLocEntry a class, reorder the members along with commentsEric Christopher2013-07-032-14/+29
| | | | | | for them and update all uses. llvm-svn: 185588
* [ARM] Improve the instruction selection of vector loads.Quentin Colombet2013-07-033-1/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | In the ARM back-end, build_vector nodes are lowered to a target specific build_vector that uses floating point type. This works well, unless the inserted bitcasts survive until instruction selection. In that case, they incur moves between integer unit and floating point unit that may result in inefficient code. In other words, this conversion may introduce artificial dependencies when the code leading to the build vector cannot be completed with a floating point type. In particular, this happens when loads are not aligned. Before this patch, in that case, the compiler generates general purpose loads and creates the floating point vector from them, instead of directly using the vector unit. The patch uses a vector friendly sequence of code when the inserted bitcasts to floating point survived DAGCombine. This is done by a target specific DAGCombine that changes the target specific build_vector into a sequence of insert_vector_elt that get rid of the bitcasts. <rdar://problem/14170854> llvm-svn: 185587
* Elaborate on comment.Eric Christopher2013-07-031-1/+1
| | | | llvm-svn: 185586
* Add names to the header file since they help in documenting the APIEric Christopher2013-07-031-10/+11
| | | | | | (and for consistency). llvm-svn: 185585
* [PowerPC] FreeBSD does not require f128 in its data layout string.Bill Schmidt2013-07-031-1/+1
| | | | | | Long double is 64 bits on FreeBSD PPC, so the f128 entry is superfluous. llvm-svn: 185583
* Add platform specific tests docRenato Golin2013-07-031-0/+60
| | | | llvm-svn: 185581
* ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying ↵Tilmann Scheller2013-07-032-9/+7
| | | | | | | | | | | | | | certain Thumb2 add immediate T3 encodings. Before the fix Thumb2 instructions of type "add rD, rN, #imm" (T3 encoding, see ARM ARM A8.8.4) with rD and rN both being low registers (r0-r7) were classified as having the T4 encoding. The T4 encoding doesn't have a cc_out operand so for above instructions the operand gets erroneously removed, corrupting the token stream and leading to parse errors later in the process. This bug prevented "add r1, r7, #0xcbcbcbcb" from being assembled correctly. Fixes <rdar://problem/14224440>. llvm-svn: 185575
* Move typedefs inside the class that they belong to.Eric Christopher2013-07-031-10/+7
| | | | llvm-svn: 185573
* Use an RWMutex instead of a Mutex in PassRegistry.Chad Rosier2013-07-031-10/+11
| | | | | | Patch by Alex Crichton <alex@crichton.co>. Approved by Chris Lattner. llvm-svn: 185566
* [PowerPC] Support lmw/stmw in the asm parserUlrich Weigand2013-07-032-1/+14
| | | | | | | This adds support for the load/store multiple instructions, currently used by the asm parser only. llvm-svn: 185564
* [PowerPC] Use mtocrf when availableUlrich Weigand2013-07-0310-25/+54
| | | | | | | | | | | | | | | | | | | | Just as with mfocrf, it is also preferable to use mtocrf instead of mtcrf when only a single CR register is to be written. Current code however always emits mtcrf. This probably does not matter when using an external assembler, since the GNU assembler will in fact automatically replace mtcrf with mtocrf when possible. It does create inefficient code with the integrated assembler, however. To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and uses those instead of MTCRF/MTCRF8 everything. Just as done in the MFOCRF patch committed as 185556, these patterns will be converted back to MTCRF if MTOCRF is not available on the machine. As a side effect, this allows to modify the MTCRF pattern to accept the full range of mask operands for the benefit of the asm parser. llvm-svn: 185561
* [PowerPC] Always use mfocrf if availableUlrich Weigand2013-07-039-65/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When accessing just a single CR register, it is always preferable to use mfocrf instead of mfcr, if the former is available on the CPU. Current code makes that distinction in many, but not all places where a single CR register value is retrieved. One missing location is PPCRegisterInfo::lowerCRSpilling. To fix this and make this simpler in the future, this patch changes the bulk of the back-end to always assume mfocrf is available and simply generate it when needed. On machines that actually do not support mfocrf, the instruction is replaced by mfcr at the very end, in EmitInstruction. This has the additional benefit that we no longer need the MFCRpseud hack, since before EmitInstruction we always have a MFOCRF instruction pattern, which already models data flow as required. The patch also adds the MFOCRF8 version of the instruction, which was missing so far. Except for the PPCRegisterInfo::lowerCRSpilling case, no change in generated code intended. llvm-svn: 185556
* Prefix failing commands with not to make clear they are expected to fail.Rafael Espindola2013-07-0326-30/+30
| | | | llvm-svn: 185554
* Remove another old test.Rafael Espindola2013-07-031-99/+0
| | | | | | | It was only passing because 'grep andpd' was not finding any andpd, but we don't fail if part of a pipe fails. llvm-svn: 185552
* Remove test for the old EH system. It doesn't parse anymore.Rafael Espindola2013-07-031-19/+0
| | | | llvm-svn: 185551
* Fix test: It was missing run lines and llvm-dis has no -disable-verify option.Rafael Espindola2013-07-031-4/+4
| | | | llvm-svn: 185550
* Add support for gnu archives with a string table and no symtab.Rafael Espindola2013-07-033-27/+60
| | | | | | While there, use early returns to reduce nesting. llvm-svn: 185547
* Make llvm-nm return 1 on error.Rafael Espindola2013-07-032-0/+25
| | | | | | | This is a small compatibility improvement with gnu nm and makes llvm-nm more useful as a testing tool. llvm-svn: 185546
* [PowerPC] Remove dead code from PPCDAGToDAGISel::SelectSETCCUlrich Weigand2013-07-031-23/+5
| | | | | | | | | | | | | | | | The subroutine getCRIdxForSetCC has a parameter "Other" and comment: If this returns with Other != -1, then the returned comparison is an or of two simpler comparisons. However for at least the last five years this routine has never returned a value of Other != -1; these cases are now handled differently to begin with. This patch removes the parameter and the code in SelectSETCC that attempted to handle the Other != -1 case. llvm-svn: 185541
* Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid ↵Craig Topper2013-07-0311-35/+35
| | | | | | specifying the vector size. llvm-svn: 185540
* Fix regular expression used by 'make update' to only look for 'I' and '?' at ↵Craig Topper2013-07-031-1/+1
| | | | | | | | the start of svn info results and to check for spaces after 'I' instead of just after '?'. Previously it was able to match 'I' anywhere in the filenames of the svn info results instead of just files that where ignored or unknown to svn. This would cause 'make update' to infinitely recurse if a file was modified with I anywhere in its name since svn info would return a Path pointing to the llvm root for those files. llvm-svn: 185539
* [msan] Unpoison stack allocations and undef values in blacklisted functions.Evgeniy Stepanov2013-07-032-10/+49
| | | | | | | This changes behavior of -msan-poison-stack=0 flag from not poisoning stack allocations to actively unpoisoning them. llvm-svn: 185538
* [PowerPC] Make specialized AltiVec patterns isCodeGenOnlyUlrich Weigand2013-07-031-2/+3
| | | | | | | | | | | A couple of AltiVec patterns are just specialized forms of the generic instruction pattern, and should therefore be marked isCodeGenOnly to avoid confusing the asm parser: VCFSX_0, VCTUXS_0, VCFUX_0, VCTSXS_0, and V_SETALLONES. Noticed by inspection of the generated PPCGenAsmMatcher.inc. llvm-svn: 185533
* [PowerPC] Support mtspr/mfspr in the asm parserUlrich Weigand2013-07-034-15/+28
| | | | | | | | | This adds support for the generic forms of mtspr/mfspr for the asm parser. The compiler will continue to use the specialized patters for mtlr etc. since those are needed to correctly describe data flow. llvm-svn: 185532
* [SystemZ] Fold more spillsRichard Sandiford2013-07-0360-251/+4023
| | | | | | | | | | | | | | | Add a mapping from register-based <INSN>R instructions to the corresponding memory-based <INSN>. Use it to cut down on the number of spill loads. Some instructions extend their operands from smaller fields, so this required a new TSFlags field to say how big the unextended operand is. This optimisation doesn't trigger for C(G)R and CL(G)R because in practice we always combine those instructions with a branch. Adding a test for every other case probably seems excessive, but it did catch a missed optimisation for DSGF (fixed in r185435). llvm-svn: 185529
* This corrects the implementation of Thumb ADR instruction. There are three ↵Mihai Popa2013-07-039-14/+62
| | | | | | | | | | issues: 1. it should accept only 4-byte aligned addresses 2. the maximum offset should be 1020 3. it should be encoded with the offset scaled by two bits llvm-svn: 185528
* ARM: relax the atomic release barrier to "dmb ishst" on SwiftTim Northover2013-07-034-57/+112
| | | | | | | | | | | Swift cores implement store barriers that are stronger than the ARM specification but weaker than general barriers. They are, in fact, just about enough to provide the ordering needed for atomic operations with release semantics. This patch makes use of that quirk. llvm-svn: 185527
* [SystemZ] Rename mapping table fieldsRichard Sandiford2013-07-032-37/+37
| | | | | | | | | | | | | Rename Function->DispKey and PairType->DispSize. I'd originally used "Function" because I thought it might be useful for other InstMappings. However, it turns out that having two very similar instructions with the same Function makes it pretty useless for anything other than the displacement size key. Other InstMappings will want the key to be defined for only one instruction in the pair. No behavioural change intended. llvm-svn: 185526
* [SystemZ] Fix caller-allocated save slot FIXMERichard Sandiford2013-07-033-46/+21
| | | | | | | Get rid of some old code (and associated FIXME) for handling the caller-allocated register save area. No behavioural change intended. llvm-svn: 185525
* Remove unused field.Eric Christopher2013-07-031-12/+19
| | | | llvm-svn: 185523
* Constify a few functions.Eric Christopher2013-07-031-3/+3
| | | | llvm-svn: 185520
* [XCore] Whitespace fixes, no functionality change.Richard Osborne2013-07-031-3/+3
| | | | llvm-svn: 185519
* [XCore] Add ISel pattern for LDWCPRichard Osborne2013-07-032-8/+16
| | | | | | Patch by Robert Lytton. llvm-svn: 185518
* Use SmallVectorImpl::const_iterator instead of SmallVector to avoid ↵Craig Topper2013-07-031-4/+4
| | | | | | specifying the vector size. llvm-svn: 185514
* Use SmallVectorImpl instead of SmallVector as method argument to avoid ↵Craig Topper2013-07-032-2/+2
| | | | | | specifying vector size. llvm-svn: 185513
* Use SmallVectorImpl instead of SmallVector for iterators and references to ↵Craig Topper2013-07-0314-41/+41
| | | | | | avoid specifying the vector size unnecessarily. llvm-svn: 185512
* Use SmallVectorImpl::iterator/const_iterator instead of SmallVectorEric Christopher2013-07-032-6/+6
| | | | | | to avoid specifying the vector size. llvm-svn: 185511
* Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid ↵Craig Topper2013-07-031-2/+2
| | | | | | specifying the vector size. llvm-svn: 185509
* Introduce some typedefs for DenseMaps containing SmallVectors so the vector ↵Craig Topper2013-07-032-7/+9
| | | | | | size doesn't have to repeated when creating iterators for the DenseMap. llvm-svn: 185508
* Return SmallVectorImpl& instead of SmallVector& in a couple places to avoid ↵Craig Topper2013-07-032-9/+9
| | | | | | having to specify the vector size in multiple places. llvm-svn: 185507
* Add a space between type and variable name. No functional change.Craig Topper2013-07-031-2/+2
| | | | llvm-svn: 185506
* Use SmallVectorImpl& instead of SmallVector& to avoid needlessly ↵Craig Topper2013-07-031-6/+6
| | | | | | respecifying the small vector size. llvm-svn: 185505
* Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid ↵Craig Topper2013-07-031-8/+8
| | | | | | specifying the vector size. llvm-svn: 185504
* Change the gettimeofday test to only test on a posix platform.Michael Gottesman2013-07-031-1/+3
| | | | llvm-svn: 185503
* Added support in FunctionAttrs for adding relevant function/argument ↵Michael Gottesman2013-07-032-0/+13
| | | | | | | | | | attributes for the posix call gettimeofday. This implies annotating it as nounwind and its arguments as nocapture. To be conservative, we do not annotate the arguments with noalias since some platforms do not have restrict on the declaration for gettimeofday. llvm-svn: 185502
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