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* Don't spill PPC VRSAVE on non-Darwin (even in SjLj)Hal Finkel2013-03-275-6/+18
| | | | | | | | | | | | | As Bill Schmidt pointed out to me, only on Darwin do we need to spill/restore VRSAVE in the SjLj code. For non-Darwin, don't spill/restore VRSAVE (and I've added some asserts to make sure that we're not). As it turns out, we're not currently handling the Darwin case correctly (I've added a FIXME in the test case). I've tried adding various implied register definitions/uses to force the spill without success, so I'll need to address this later. llvm-svn: 178096
* Make DIBuilder::createClassType more type safe by returning DICompositeType ↵David Blaikie2013-03-262-14/+17
| | | | | | rather than DIType llvm-svn: 178091
* DebugInfo: more support for mutating DICompositeType to reduce magic number ↵David Blaikie2013-03-262-1/+9
| | | | | | usage in Clang llvm-svn: 178090
* Add a boolean parameter to the ExecuteAndWait static function to indicatedChad Rosier2013-03-262-5/+9
| | | | | | | | | | if execution failed. ExecuteAndWait returns -1 upon an execution failure, but checking the return value isn't sufficient because the wait command may return -1 as well. This new parameter is to be used by the clang driver in a subsequent commit. Part of rdar://13362359 llvm-svn: 178087
* Use the full path when outputting the `.gcda' file.Bill Wendling2013-03-261-5/+14
| | | | | | | | | | | | | | If we compile a single source program, the `.gcda' file will be generated where the program was executed. This isn't desirable, because that place may be at an unpredictable place (the program could call `chdir' for instance). Instead, we will output the `.gcda' file in the same place we output the `.gcno' file. I.e., the directory where the executable was generated. This matches GCC's behavior. <rdar://problem/13061072> & PR11809 llvm-svn: 178084
* Add XTEST codegen supportMichael Liao2013-03-266-1/+35
| | | | llvm-svn: 178083
* Add HLE target featureMichael Liao2013-03-264-1/+14
| | | | llvm-svn: 178082
* Enable SandyBridgeModel for all modern Intel P6 descendants.Jakob Stoklund Olesen2013-03-264-37/+47
| | | | | | | | | | | | All Intel CPUs since Yonah look a lot alike, at least at the granularity of the scheduling models. We can add more accurate models for processors that aren't Sandy Bridge if required. Haswell will probably need its own. The Atom processor and anything based on NetBurst is completely different. So are the non-Intel chips. llvm-svn: 178080
* Debug Info: Provide a means to update the members of a composite typeDavid Blaikie2013-03-262-0/+12
| | | | | | | | This will be used to factor out some uses of magic number operand offsets inside Clang where these fields were updated in an effort to resolve forward declarations/circular references. llvm-svn: 178078
* Restore real bit lengths on PPC register numbersHal Finkel2013-03-261-12/+12
| | | | | | | | | | As suggested by Bill Schmidt (in reviewing r178067), use the real register number bit lengths (which is self-documenting, and prevents using illegal numbers), and set only the relevant bits in HWEncoding (which defaults to 0). No functionality change intended. llvm-svn: 178077
* TableGen SubtargetEmitter fix to allow A9 and Swift to coexist.Andrew Trick2013-03-262-2/+24
| | | | | | Allow variants to be defined only for some processors on a target. llvm-svn: 178074
* Fix the register scavenger for targets that provide custom spillingHal Finkel2013-03-262-4/+8
| | | | | | | | | | | As pointed out by Richard Sandiford, my recent updates to the register scavenger broke targets that use custom spilling (because the new code assumed that if there were no valid spill slots, than spilling would be impossible). I don't have a test case, but it should be possible to create one for Thumb 1, Mips 16, etc. llvm-svn: 178073
* PPC: Use HWEncoding and TRI->getEncodingValueHal Finkel2013-03-268-100/+31
| | | | | | | | | | | As pointed out by Jakob, we don't need to maintain a separate register-numbering table. Instead we should let TableGen generate the table for us from the information (already present) in PPCRegisterInfo.td. TRI->getEncodingValue is now used to access register-encoding values. No functionality change intended. llvm-svn: 178067
* R600/SIMCCodeEmitter.cpp: Prune a couple of unused members, STI and Ctx. ↵NAKAMURA Takumi2013-03-261-3/+1
| | | | | | [-Wunused-private-field] llvm-svn: 178065
* Use multiple virtual registers in PPC CR spillingHal Finkel2013-03-263-42/+58
| | | | | | | | | | | | Now that the register scavenger can support multiple spill slots, and PEI can use virtual-register-based scavenging for multiple simultaneous registers, we can use a virtual register for the transfer register in the CR spilling code. This should eliminate the last place (outside of the prologue/epilogue) where we depend on the unconditional availability of the r0 register. We will soon be able to allocate it (in a somewhat restricted sense) as a GPR. llvm-svn: 178060
* Update PPCRegisterInfo's use of virtual registers to be SSAHal Finkel2013-03-261-3/+5
| | | | | | | | | | | PPC's use of PEI's virtual-register-based scavenging functionality had redefined the virtual registers (it was non-SSA). Now that PEI supports dealing with instructions with multiple virtual registers, this can be cleanup up to use multiple virtual registers and keep SSA form. No functionality change intended. llvm-svn: 178059
* Update PEI's virtual-register-based scavenging to support multiple ↵Hal Finkel2013-03-264-27/+43
| | | | | | | | | | | | | | | | | | | simultaneous mappings The previous algorithm could not deal properly with scavenging multiple virtual registers because it kept only one live virtual -> physical mapping (and iterated through operands in order). Now we don't maintain a current mapping, but rather use replaceRegWith to completely remove the virtual register as soon as the mapping is established. In order to allow the register scavenger to return a physical register killed by an instruction for definition by that same instruction, we now call RS->forward(I) prior to eliminating virtual registers defined in I. This requires a minor update to forward to ignore virtual registers. These new features will be tested in forthcoming commits. llvm-svn: 178058
* Annotate the remaining x86 instructions with SchedRW lists.Jakob Stoklund Olesen2013-03-263-10/+10
| | | | | | | | | | Now all x86 instructions that have itinerary classes also have SchedRW lists. This is required before the new scheduling models can be used. There are still unannotated instructions remaining, but they don't have itinerary classes either. llvm-svn: 178051
* Annotate x87 and mmx instructions with SchedRW lists.Jakob Stoklund Olesen2013-03-262-31/+71
| | | | | | | This only covers the instructions that were given itinerary classes for the Atom model. llvm-svn: 178050
* Annotate control instructions with SchedRW lists.Jakob Stoklund Olesen2013-03-261-28/+41
| | | | | | | This could definitely be more granular. I am not sure if it makes a difference. llvm-svn: 178049
* Annotate the rest of X86InstrInfo.td with SchedRW lists.Jakob Stoklund Olesen2013-03-261-27/+43
| | | | llvm-svn: 178048
* Fix PRFCHW test on non-x86 buildsMichael Liao2013-03-261-1/+1
| | | | | | | - 'prefetch' intrinsics are only lowered when SSE is available. On non-X86 builds, 'generic' CPU is used and stops lowering any prefetch intrinsics. llvm-svn: 178046
* BasicAA: Only query twice if the result of the more general query was MayAliasArnold Schwaighofer2013-03-261-5/+5
| | | | | | | | | | | | | | This is a compile time optimization. Before the patch we would do two traversals on each call to aliasGEP - one with a set size parameter one with UnknownSize. We can do better by first checking the result of the alias query with UnknownSize. Only if this one returns MayAlias do we query a second time using size and type. This recovers an about 7% compile time regression on spec/ammp. radar://12349960 llvm-svn: 178045
* Add PREFETCHW codegen supportMichael Liao2013-03-266-5/+24
| | | | | | - Add 'PRFCHW' feature defined in AVX2 ISA extension llvm-svn: 178040
* Add test case for commit r178031.Ulrich Weigand2013-03-261-0/+50
| | | | llvm-svn: 178038
* Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.Jyotsna Verma2013-03-263-186/+69
| | | | llvm-svn: 178032
* Make InstCombineCasts.cpp:OptimizeIntToFloatBitCast endian safe.Ulrich Weigand2013-03-261-1/+9
| | | | | | | | | | | | | The OptimizeIntToFloatBitCast converts shift-truncate sequences into extractelement operations. The computation of the element index to be used in the resulting operation is currently only correct for little-endian targets. This commit fixes the element index computation to be correct for big-endian targets as well. If the target byte order is unknown, the optimization cannot be performed at all. llvm-svn: 178031
* Hexagon: Remove HexagonMCInst.h file. It has been replaced with ↵Jyotsna Verma2013-03-261-41/+0
| | | | | | MCTargetDesc/HexagonMCInst.h. llvm-svn: 178030
* Revert ARM Scheduler Model: Add resources instructions, map resourcesArnold Schwaighofer2013-03-264-70/+24
| | | | | | | | | | | | | This reverts commit r177968. It is causing failures in a local build bot. "fatal error: error in backend: Expected a variant SchedClass" Original commit message: Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. llvm-svn: 178028
* Remove default case from fully covered switch.Benjamin Kramer2013-03-261-1/+1
| | | | llvm-svn: 178025
* R600/SI: improve post ISel foldingChristian Konig2013-03-261-31/+43
| | | | | | | Not only fold immediates, but avoid unnecessary copies as well. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178024
* R600/SI: improve vector interpolationChristian Konig2013-03-261-0/+20
| | | | | | | Prevent loading M0 multiple times. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178023
* R600/SI: avoid unecessary subreg extraction in IMAGE_SAMPLEChristian Konig2013-03-262-14/+8
| | | | | | | Just define the address as unknown instead of VReg_32. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178022
* R600/SI: switch back to RegPressure schedulingChristian Konig2013-03-263-1/+9
| | | | | Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178021
* R600/SI: mark most intrinsics as readnone v2Christian Konig2013-03-263-54/+89
| | | | | | | | | They read from constant register space anyway. v2: fix lit tests Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178020
* R600/SI: replace WQM intrinsicChristian Konig2013-03-265-28/+14
| | | | | | | Just enable WQM when we see an LDS interpolation instruction. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178019
* R600/SI: fix ELSE pseudo op handlingChristian Konig2013-03-261-1/+2
| | | | | | | | | | | Restore the EXEC mask early, otherwise a copy might end up not beeing executed. Candidate for the mesa stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178018
* Patch by Gordon Keiser!Joe Abbey2013-03-262-1/+3
| | | | | | | | | | If PC or SP is the destination, the disassembler erroneously failed with the invalid encoding, despite the manual saying that both are fine. This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a postindexed load, where the offset 0xc is applied to SP after the load occurs. llvm-svn: 178017
* [ASan] Change the ABI of __asan_before_dynamic_init function: now it takes ↵Alexey Samsonov2013-03-261-17/+13
| | | | | | pointer to private string with module name. This string serves as a unique module ID in ASan runtime. LLVM part llvm-svn: 178013
* PowerPC: Mark patterns as isCodeGenOnly.Ulrich Weigand2013-03-264-7/+21
| | | | | | | | | | | There remain a number of patterns that cannot (and should not) be handled by the asm parser, in particular all the Pseudo patterns. This commit marks those patterns as isCodeGenOnly. No change in generated code. llvm-svn: 178008
* PowerPC: Simplify handling of fixups.Ulrich Weigand2013-03-265-70/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MCTargetDesc/PPCMCCodeEmitter.cpp current has code like: if (isSVR4ABI() && is64BitMode()) Fixups.push_back(MCFixup::Create(0, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_toc16)); else Fixups.push_back(MCFixup::Create(0, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_lo16)); This is a problem for the asm parser, since it requires knowledge of the ABI / 64-bit mode to be set up. However, more fundamentally, at this point we shouldn't make such distinctions anyway; in an assembler file, it always ought to be possible to e.g. generate TOC relocations even when the main ABI is one that doesn't use TOC. Fortunately, this is actually completely unnecessary; that code was added to decide whether to generate TOC relocations, but that information is in fact already encoded in the VariantKind of the underlying symbol. This commit therefore merges those fixup types into one, and then decides which relocation to use based on the VariantKind. No changes in generated code. llvm-svn: 178007
* PowerPC: Simplify FADD in round-to-zero mode.Ulrich Weigand2013-03-264-101/+50
| | | | | | | | | | | | | | | | | | | | | | | As part of the the sequence generated to implement long double -> int conversions, we need to perform an FADD in round-to-zero mode. This is problematical since the FPSCR is not at all modeled at the SelectionDAG level, and thus there is a risk of getting floating point instructions generated out of sequence with the instructions to modify FPSCR. The current code handles this by somewhat "special" patterns that in part have dummy operands, and/or duplicate existing instructions, making them awkward to handle in the asm parser. This commit changes this by leaving the "FADD in round-to-zero mode" as an atomic operation on the SelectionDAG level, and only split it up into real instructions at the MI level (via custom inserter). Since at *this* level the FPSCR *is* modeled (via the "RM" hard register), much of the "special" stuff can just go away, and the resulting patterns can be used by the asm parser. No significant change in generated code expected. llvm-svn: 178006
* PowerPC: Remove LDrs pattern.Ulrich Weigand2013-03-263-16/+9
| | | | | | | | | | | | | | | | | | | | The LDrs pattern is a duplicate of LD, except that it accepts memory addresses where the displacement is a symbolLo64. An operand type "memrs" is defined for just that purpose. However, this wouldn't be necessary if the default "memrix" operand type were to simply accept 64-bit symbolic addresses directly. The only problem with that is that it uses "symbolLo", which is hardcoded to 32-bit. To fix this, this commit changes "memri" and "memrix" to use new operand types for the memory displacement, which allow iPTR instead of i32. This will also make address parsing easier to implment in the asm parser. No change in generated code. llvm-svn: 178005
* PowerPC: Remove ADDIL patterns.Ulrich Weigand2013-03-264-20/+13
| | | | | | | | | | | | | | The ADDI/ADDI8 patterns are currently duplicated into ADDIL/ADDI8L, which describe the same instruction, except that they accept a symbolLo[64] operand instead of a s16imm[64] operand. This duplication confuses the asm parser, and it actually not really needed, since symbolLo[64] already accepts immediate operands anyway. So this commit removes the duplicate patterns. No change in generated code. llvm-svn: 178004
* PowerPC: Use CCBITRC operand for ISEL patterns.Ulrich Weigand2013-03-265-46/+19
| | | | | | | | | | | | This commit changes the ISEL patterns to use a CCBITRC operand instead of a "pred" operand. This matches the actual instruction text more directly, and simplifies use of ISEL with the asm parser. In addition, this change allows some simplification of handling the "pred" operand, as this is now only used by BCC. No change in generated code. llvm-svn: 178003
* PowerPC: Simplify BLR pattern.Ulrich Weigand2013-03-263-12/+6
| | | | | | | | | | | | | | | | | The BLR pattern cannot be recognized by the asm parser in its current form. This complexity is due to an apparent attempt to enable conditional BLR variants. However, none of those can ever be generated by current code; the pattern is only ever created using the default "pred" operand. To simplify the pattern and allow it to be recognized by the parser, this commit removes those attempts at conditional BLR support. When we later come back to actually add real conditional BLR, this should probably be done via a fully generic conditional branch pattern. No change in generated code. llvm-svn: 178002
* PowerPC: Move some 64-bit branch patterns.Ulrich Weigand2013-03-261-17/+18
| | | | | | | | | | | | In PPCInstr64Bit.td, some branch patterns appear in a different sequence than the corresponding 32-bit patterns in PPCInstrInfo.td. To simplify future changes that affect both files, this commit moves those patterns to rearrange them into a similar sequence. No effect on generated code. llvm-svn: 178001
* R600: fix DenseMap with pointer key iteration in the structurizerChristian Konig2013-03-261-2/+4
| | | | | | | | | Use a MapVector on types where the iteration order matters. Otherwise we doesn't always produce a deterministic output. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 177999
* Add asan/msan to the list of available features in LIT test runnerAlexey Samsonov2013-03-262-0/+8
| | | | llvm-svn: 177994
* Add CMake option LLVM_USE_SANITIZER={Address,Memory,MemoryWithOrigins} to ↵Alexey Samsonov2013-03-262-3/+45
| | | | | | simplify bootstrap of LLVM/Clang under ASan/MSan llvm-svn: 177992
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