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* Guard fields by NDEBUG until they get used in the release build.Andrew Trick2012-09-161-2/+2
| | | | llvm-svn: 163993
* Tidy up formatting of some elses on a separate line from preceding bracing. ↵Craig Topper2012-09-161-5/+5
| | | | | | No functional change. llvm-svn: 163992
* Add alternative coalescing algorithm under a flag.Jakob Stoklund Olesen2012-09-161-0/+478
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The live range of an SSA value forms a sub-tree of the dominator tree. That means the live ranges of two values overlap if and only if the def of one value lies within the live range of the other. This can be used to simplify the interference checking a bit: Visit each def in the two registers about to be joined. Check for interference against the value that is live in the other register at the def point only. It is not necessary to scan the set of overlapping live ranges, this interference check can be done while computing the value mapping required for the final live range join. The new algorithm is prepared to handle more complicated conflict resolution - We can allow overlapping live ranges with different values as long as the differing lanes are undef or unused in the other register. The implementation in this patch doesn't do that yet, it creates code that is nearly identical to the old algorithm's, except: - The new stripCopies() function sees through multiple copies while the old RegistersDefinedFromSameValue() only can handle one. - There are a few rare cases where the new algorithm can erase an IMPLICIT_DEF instuction that RegistersDefinedFromSameValue() couldn't handle. llvm-svn: 163991
* Fix problem when using LiveRangeQuery with block entries.Jakob Stoklund Olesen2012-09-161-1/+3
| | | | | | | | | | A value that is live in to a basic block should be returned by valueIn() in LiveRangeQuery(getMBBStartIdx(MBB)), unless it is a PHI-def which should be returned by valueDefined() instead. Current code isn't using this functionality. Future code will. llvm-svn: 163990
* Tidy up trailing whitespace.Craig Topper2012-09-161-32/+32
| | | | llvm-svn: 163988
* Remove unneeded header.Craig Topper2012-09-161-1/+0
| | | | llvm-svn: 163987
* Fix Doxygen issues: wrap code examples in \code and use \p to refer toDmitri Gribenko2012-09-153-5/+8
| | | | | | parameters. llvm-svn: 163984
* Fix includes of llvm files that used angle brackets.Craig Topper2012-09-154-16/+16
| | | | llvm-svn: 163979
* Fix a couple include directives that used angle brackets for llvm files.Craig Topper2012-09-152-2/+2
| | | | llvm-svn: 163978
* Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.Craig Topper2012-09-1514-38/+41
| | | | llvm-svn: 163974
* Remove unused private fields to silence -Wunused-private-field.Craig Topper2012-09-151-9/+6
| | | | llvm-svn: 163973
* Don't depend on kill flags in removeCopyByCommutingDef().Jakob Stoklund Olesen2012-09-151-1/+1
| | | | | | | Kill flags are removed more and more aggressively during the register allocation passes, it is better to get information from LiveIntervals. llvm-svn: 163972
* Make LiveRangeQuery work for PHIDefs as well.Jakob Stoklund Olesen2012-09-151-0/+6
| | | | | | | | | | | | | | If a PHI value happens to be live out from the layout predecessor of its def block, the def slot index will be in the middle of the segment: %vreg11 = [192r,240B:0)[352r,416B:2)[416B,496r:1) 0@192r 1@480B-phi %2@352r A LiveRangeQuery for 480 should return NULL from valueIn() since the PHI value is defined at the block entry, not live in to the block. No test case, future code depends on this functionality. llvm-svn: 163971
* Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.Craig Topper2012-09-151-2/+2
| | | | llvm-svn: 163970
* Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.Craig Topper2012-09-152-6/+6
| | | | llvm-svn: 163969
* Disable new sroa now that all buildbots have tested it.Benjamin Kramer2012-09-151-1/+1
| | | | | | | | | | | | | | | | | What we have so far: - Some clang test failures (these were known already) - Perf results are mixed, some big regressions http://llvm.org/perf/db_default/v4/nts/3844 http://llvm.org/perf/db_default/v4/nts/3845 bullet suffers a lot. matmul is interesting: slower scalar code, faster with -vectorize. - Some dragonegg selfhost bots crash in SROA during selfhost now http://lab.llvm.org:8011/builders/dragonegg-x86_64-linux-gcc-4.6-self-host-checks/builds/1632 http://lab.llvm.org:8011/builders/dragonegg-x86_64-linux-gcc-4.5-self-host/builds/1891 llvm-svn: 163968
* X86: Emitting x87 fsin/fcos for sinf/cosf is not safe without unsafe fp math.Benjamin Kramer2012-09-152-0/+15
| | | | | | This was only an issue if sse is disabled. llvm-svn: 163967
* Port the SSAUpdater-based promotion logic from the old SROA pass to theChandler Carruth2012-09-154-15/+182
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | new one, and add support for running the new pass in that mode and in that slot of the pass manager. With this the new pass can completely replace the old one within the pipeline. The strategy for enabling or disabling the SSAUpdater logic is to do it by making the requirement of the domtree analysis optional. By default, it is required and we get the standard mem2reg approach. This is usually the desired strategy when run in stand-alone situations. Within the CGSCC pass manager, we disable requiring of the domtree analysis and consequentially trigger fallback to the SSAUpdater promotion. In theory this would allow the pass to re-use a domtree if one happened to be available even when run in a mode that doesn't require it. In practice, it lets us have a single pass rather than two which was simpler for me to wrap my head around. There is a hidden flag to force the use of the SSAUpdater code path for the purpose of testing. The primary testing strategy is just to run the existing tests through that path. One notable difference is that it has custom code to handle lifetime markers, and one of the tests has been enhanced to exercise that code. This has survived a bootstrap and the test suite without serious correctness issues, however my run of the test suite produced *very* alarming performance numbers. I don't entirely understand or trust them though, so more investigation is on-going. To aid my understanding of the performance impact of the new SROA now that it runs throughout the optimization pipeline, I'm enabling it by default in this commit, and will disable it again once the LNT bots have picked up one iteration with it. I want to get those bots (which are much more stable) to evaluate the impact of the change before I jump to any conclusions. NOTE: Several Clang tests will fail because they run -O3 and check the result's order of output. They'll go back to passing once I disable it again. llvm-svn: 163965
* Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td andAkira Hatanaka2012-09-156-146/+52
| | | | | | | | | | use load/store fragments defined in TargetSelectionDAG.td in place of them. Unaligned loads/stores are either expanded or lowered to target-specific nodes, so instruction selection should see only aligned load/store nodes. No changes in functionality. llvm-svn: 163960
* Revert r163878 as it breaks on targets with alternate register names. Such ↵Craig Topper2012-09-152-6/+4
| | | | | | targets do not exist in the main tree so this was not noticed. llvm-svn: 163959
* Handled unaligned load/stores properly in Mips16 Akira Hatanaka2012-09-152-2/+22
| | | | | | Patch by Reed Kotler. llvm-svn: 163956
* PGO: preserve branch-weight metadata when simplifying two branches with a commonManman Ren2012-09-152-112/+64
| | | | | | | | | | | | | | | | destination. Updated previous implementation to fix a case not covered: // PBI: br i1 %x, TrueDest, BB // BI: br i1 %y, TrueDest, FalseDest The other case was handled correctly. // PBI: br i1 %x, BB, FalseDest // BI: br i1 %y, TrueDest, FalseDest Also tried to use 64-bit arithmetic instead of APInt with scale to simplify the computation. Let me know if you have other opinions about this. llvm-svn: 163954
* TableGen subtarget parser. Handle new machine model.Andrew Trick2012-09-152-0/+219
| | | | | | Collect processor resources from the subtarget defs. llvm-svn: 163953
* TableGen subtarget parser. Handle new machine model.Andrew Trick2012-09-152-0/+512
| | | | | | Infer SchedClasses from variants defined by the target or subtarget. llvm-svn: 163952
* TableGen subtarget parser. Handle new machine model.Andrew Trick2012-09-153-137/+816
| | | | | | Collect SchedClasses and SchedRW types from the subtarget defs. llvm-svn: 163951
* cmake: Fix file path.Daniel Dunbar2012-09-141-1/+1
| | | | llvm-svn: 163950
* formatted_raw_ostream: Fix a serious bug in tell().Daniel Dunbar2012-09-143-4/+39
| | | | | | | | | - The current_pos function is supposed to return all the written bytes, not the current position of the underlying stream. - This caused tell() to be broken whenever the underlying stream had buffered content. llvm-svn: 163948
* Some small reorganization to get read for Attributes overhaul.Bill Wendling2012-09-141-49/+50
| | | | llvm-svn: 163947
* Remove comment.Bill Wendling2012-09-141-1/+1
| | | | llvm-svn: 163945
* Fix up erroneous alignas usage while making this portable to GCC 4.7David Blaikie2012-09-142-94/+61
| | | | | | Review by Chandler Carruth. llvm-svn: 163944
* PGO: preserve branch-weight metadata when simplifying a switch with a singleManman Ren2012-09-143-3/+82
| | | | | | case to a conditional branch and when removing dead cases. llvm-svn: 163942
* Stylistic and 80-col fixesEvan Cheng2012-09-143-9/+5
| | | | llvm-svn: 163940
* comment typoAndrew Trick2012-09-141-1/+1
| | | | llvm-svn: 163935
* TargetSchedModel interface. To be implemented...Andrew Trick2012-09-146-0/+107
| | | | llvm-svn: 163934
* Define MC data tables for the new scheduling machine model.Andrew Trick2012-09-143-11/+167
| | | | llvm-svn: 163933
* whitespaceAndrew Trick2012-09-141-2/+2
| | | | llvm-svn: 163932
* Review feedback from Duncan Sands. Alphabetize includes and simplifyAlex Rosenberg2012-09-142-4/+4
| | | | | | lit config. llvm-svn: 163928
* Try to fix the bots by detecting inconsistant branch-weight metadata.Manman Ren2012-09-141-4/+10
| | | | llvm-svn: 163926
* Implement getNumLDMAddresses and expose through ARMBaseInstrInfo.Andrew Trick2012-09-142-0/+34
| | | | llvm-svn: 163922
* Cortex-A9 instruction-level scheduling machine model.Andrew Trick2012-09-141-3/+594
| | | | | | | | | | | | | | | | | | | | This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
* PGO: preserve branch-weight metadata when merging two switches whereManman Ren2012-09-142-5/+60
| | | | | | | the default target of the first switch is not the basic block the second switch is in (PredDefault != BB). llvm-svn: 163916
* misched: add a hook for custom DAG postprocessing.Andrew Trick2012-09-142-0/+31
| | | | llvm-svn: 163915
* Add in comments that explain what the indexing and the size of the arrays is ↵Micah Villmow2012-09-141-1/+10
| | | | | | about. llvm-svn: 163904
* DAG post-process for Hexagon MI schedulerSergei Larin2012-09-142-0/+34
| | | | | | | | This patch introduces a possibility for Hexagon MI scheduler to perform some target specific post- processing on the scheduling DAG prior to scheduling. llvm-svn: 163903
* Fix Doxygen issues:Dmitri Gribenko2012-09-1430-95/+113
| | | | | | | | | | * wrap code blocks in \code ... \endcode; * refer to parameter names in paragraphs correctly (\arg is not what most people want -- it starts a new paragraph); * use \param instead of \arg to document parameters in order to be consistent with the rest of the codebase. llvm-svn: 163902
* SROA: Silence unused variable warnings in Release builds.Benjamin Kramer2012-09-141-1/+8
| | | | | | The NDEBUG hack is ugly, but I see no better solution. llvm-svn: 163900
* Remove redundant private field.Benjamin Kramer2012-09-142-3/+2
| | | | | | clang warned about this being unused in Release builds. llvm-svn: 163899
* Rework the computation of a sub-structure natural type. There wereChandler Carruth2012-09-141-10/+20
| | | | | | | | | | | | | pointless checks in here, bad asserts, and just confusing code. I've also added a bit more to the comment to clarify what this function is really trying to do as it was not obvious to Duncan when studying it. Thanks to Duncan for helping me dig through the issue. No real functionality changed here in practical cases, and certainly no test case. This is just cleanup spotted by inspection. llvm-svn: 163897
* Rely on the recursive check for pointer types rather than adding anChandler Carruth2012-09-141-3/+0
| | | | | | | explicit check before recursing. A simplification requested by Duncan during review. llvm-svn: 163896
* Be a bit more aggressive in bailing out of this routine. Spotted byChandler Carruth2012-09-141-1/+1
| | | | | | | inspection by Duncan during review. My suspicion is that we would still have returned 0 anyways in this case, but doing it sooner is better. llvm-svn: 163895
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