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* Add support for returning multiple vectors via sret, which is how the ARM ↵Nate Begeman2010-06-201-30/+42
| | | | | | target expects the intrinsics to work. llvm-svn: 106406
* Fix warning in no-asserts build.Nick Lewycky2010-06-201-0/+1
| | | | llvm-svn: 106405
* Fix a crash caused by dereference of MBB.end(). rdar://8110842Evan Cheng2010-06-202-6/+43
| | | | llvm-svn: 106399
* Restore a call to rememberInstruction which was accidentally droppedDan Gohman2010-06-191-0/+1
| | | | | | in refactoring. llvm-svn: 106398
* Add a TODO comment.Dan Gohman2010-06-191-0/+2
| | | | llvm-svn: 106397
* Include the use kind along with the expression in the key of theDan Gohman2010-06-192-2/+337
| | | | | | | | | | | | use sharing map. The reconcileNewOffset logic already forces a separate use if the kinds differ, so incorporating the kind in the key means we can track more sharing opportunities. More sharing means fewer total uses to track, which means smaller problem sizes, which means the conservative throttles don't kick in as often. llvm-svn: 106396
* Don't include things in anonymous namespaces that don't need it.Dan Gohman2010-06-191-0/+4
| | | | llvm-svn: 106395
* Use calloc instead of new/memset, it is more efficient when the set is very ↵Benjamin Kramer2010-06-191-6/+14
| | | | | | large. llvm-svn: 106390
* Fix ScalarEvolution's "exhaustive" trip count evaluation code to avoidDan Gohman2010-06-192-2/+36
| | | | | | | | assuming that loops are in canonical form, as ScalarEvolution doesn't depend on LoopSimplify itself. Also, with indirectbr not all loops can be simplified. This fixes PR7416. llvm-svn: 106389
* Factor out duplicated code for reusing and inserting casts intoDan Gohman2010-06-192-54/+54
| | | | | | a helper function. llvm-svn: 106388
* Tidy.Bob Wilson2010-06-193-8/+8
| | | | llvm-svn: 106383
* Remove a fixme comment that is no longer relevant.Bob Wilson2010-06-191-3/+0
| | | | llvm-svn: 106382
* Fix error message to match function name.Bob Wilson2010-06-191-1/+1
| | | | llvm-svn: 106381
* Refactoring of regular logical packed instructions to prepare for AVX ones.Bruno Cardoso Lopes2010-06-191-38/+39
| | | | llvm-svn: 106375
* Refactor aliased packed logical instructions, also addBruno Cardoso Lopes2010-06-193-39/+154
| | | | | | AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions. llvm-svn: 106374
* Ignore dbg_value's.Evan Cheng2010-06-191-1/+3
| | | | llvm-svn: 106373
* Move new sse 1 & 2 generic classes to a more appropriate placeBruno Cardoso Lopes2010-06-191-61/+65
| | | | llvm-svn: 106372
* Remove unnecessary argumentsBruno Cardoso Lopes2010-06-191-4/+4
| | | | llvm-svn: 106371
* Add AVX packed intrinsics for MIN, MAXBruno Cardoso Lopes2010-06-191-37/+33
| | | | llvm-svn: 106370
* Disable sibcall optimization for Thumb1 for now since ↵Evan Cheng2010-06-194-13/+33
| | | | | | Thumb1RegisterInfo::emitEpilogue is not expecting them. llvm-svn: 106368
* Finish ripping isTwoAddress out of X86. Some mindless formattingEric Christopher2010-06-191-132/+153
| | | | | | | | | | and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
* Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructionsBruno Cardoso Lopes2010-06-193-59/+92
| | | | llvm-svn: 106366
* rip out dead code.Chris Lattner2010-06-191-6/+0
| | | | llvm-svn: 106365
* fix rdar://7873482 by teaching the instruction encoder to emitChris Lattner2010-06-193-9/+54
| | | | | | segment prefixes. Daniel wrote most of this patch. llvm-svn: 106364
* Indentation and remove dead code.Evan Cheng2010-06-191-58/+44
| | | | llvm-svn: 106362
* Clean up: remove now unnecessary ConstraintsBruno Cardoso Lopes2010-06-191-3/+1
| | | | llvm-svn: 106361
* Silence compiler warnings.Dan Gohman2010-06-191-3/+3
| | | | llvm-svn: 106360
* more refactoring! yay! big win over the intrinsicsBruno Cardoso Lopes2010-06-191-70/+30
| | | | llvm-svn: 106359
* Remove isTwoAddress from here too.Eric Christopher2010-06-181-2/+2
| | | | llvm-svn: 106358
* Fix typo, SSE1 should be used by XS, not SSE2Bruno Cardoso Lopes2010-06-181-1/+1
| | | | llvm-svn: 106357
* Remove isTwoAddress from 64-bit files.Eric Christopher2010-06-181-15/+15
| | | | llvm-svn: 106356
* Move ARM if-conversion before post-ra scheduling.Evan Cheng2010-06-182-16/+3
| | | | llvm-svn: 106355
* Teach regular and fast isel to set dead flags on unused implicit defsDan Gohman2010-06-187-0/+69
| | | | | | on calls and similar instructions. llvm-svn: 106353
* Apply some refactor to packed instructionsBruno Cardoso Lopes2010-06-182-62/+42
| | | | llvm-svn: 106349
* Update cmake list.Evan Cheng2010-06-181-0/+1
| | | | llvm-svn: 106348
* Thumb2 hazard recognizer.Evan Cheng2010-06-182-0/+90
| | | | llvm-svn: 106347
* Only run CoalesceExtSubRegs when we can expect LiveIntervalAnalysis to clean upJakob Stoklund Olesen2010-06-181-2/+5
| | | | | | the inserted INSERT_SUBREGs after us. llvm-svn: 106345
* Allow ARM if-converter to be run after post allocation scheduling.Evan Cheng2010-06-1818-82/+302
| | | | | | | | | | | | | | | | - This fixed a number of bugs in if-converter, tail merging, and post-allocation scheduler. If-converter now runs branch folding / tail merging first to maximize if-conversion opportunities. - Also changed the t2IT instruction slightly. It now defines the ITSTATE register which is read by instructions in the IT block. - Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't change the instruction ordering in the IT block (since IT mask has been finalized). It also ensures no other instructions can be scheduled between instructions in the IT block. This is not yet enabled. llvm-svn: 106344
* back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)Jim Grosbach2010-06-184-0/+21
| | | | llvm-svn: 106342
* Another typo.Eric Christopher2010-06-181-1/+1
| | | | llvm-svn: 106340
* Enable Expand handling of atomics for subtargets that can't do them inline.Jim Grosbach2010-06-181-3/+39
| | | | llvm-svn: 106336
* Fix typo.Eric Christopher2010-06-181-1/+1
| | | | llvm-svn: 106335
* TwoAddressInstructionPass::CoalesceExtSubRegs can insert INSERT_SUBREGJakob Stoklund Olesen2010-06-182-1/+36
| | | | | | | | | instructions, but it doesn't really understand live ranges, so the first INSERT_SUBREG uses an implicitly defined register. Fix it in LiveVariableAnalysis by adding the <undef> flag. llvm-svn: 106333
* Fix an inverted condition.Evan Cheng2010-06-184-5/+3
| | | | llvm-svn: 106330
* Use the new 'defm' class inheritance in SSEBruno Cardoso Lopes2010-06-181-32/+24
| | | | llvm-svn: 106327
* Fix cross initialization compilation error.Evan Cheng2010-06-181-1/+2
| | | | llvm-svn: 106324
* Teach iff-converter to properly count # of dups. It was not skipping over ↵Evan Cheng2010-06-181-1/+27
| | | | | | dbg_value's which resulted in non-duplicated instructions being deleted. rdar://8104384. llvm-svn: 106323
* Add Expand-to-libcall support for additional atomics. This covers the usualJim Grosbach2010-06-183-4/+182
| | | | | | | | | | entries used by llvm-gcc. *_[U]MIN and such can be added later if needed. This enables the front ends to simplify handling of the atomic intrinsics by removing the target-specific decision about which targets can handle the intrinsics. llvm-svn: 106321
* Rewrite chained if's as switches and replace assertions with llvm_unreachableBob Wilson2010-06-181-35/+55
| | | | | | (as suggested in radar 8104405). llvm-svn: 106318
* Fix ARM/Thumb reversal in previous attempt.Dale Johannesen2010-06-181-2/+2
| | | | llvm-svn: 106314
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