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* [PM] Fix a small typo from when I ported JumpThreadingSean Silva2016-07-021-1/+1
| | | | llvm-svn: 274440
* [X86][AVX512] Autoupgrade the MOVDDUP/MOVSLDUP/MOVSHDUP intrinsicsSimon Pilgrim2016-07-025-204/+227
| | | | llvm-svn: 274439
* [DIBuilder] Remove dead code. NFC.Benjamin Kramer2016-07-021-34/+0
| | | | llvm-svn: 274438
* [Hexagon] Create global std::map lazily.Benjamin Kramer2016-07-021-3/+3
| | | | | | | | This could of course be a simple binary search with no global state involved at all if someone cares enough. Just don't make everyone linking the hexagon backend pay for it on process startup and shutdown. llvm-svn: 274437
* [X86][AVX512] Add support for lowering shuffles to MOVDDUP/MOVSLDUP/MOVSHDUPSimon Pilgrim2016-07-023-8/+23
| | | | llvm-svn: 274436
* [X86][AVX512] Add test cases that should lower to MOVSLDUP/MOVSHDUPSimon Pilgrim2016-07-021-1/+21
| | | | llvm-svn: 274435
* [X86][AVX512] Add fast-isel shuffle testsSimon Pilgrim2016-07-022-0/+737
| | | | | | Its not worth trying to write out tests for all the avx512f builtins yet, just adding tests for lowering of generic IR as we transition to it (shuffles mainly right now). llvm-svn: 274434
* Use arrays or initializer lists to feed ArrayRefs instead of SmallVector ↵Benjamin Kramer2016-07-029-55/+28
| | | | | | | | where possible. No functionality change intended. llvm-svn: 274431
* [esan|cfrag] Add counters for struct array accessesQin Zhao2016-07-023-72/+143
| | | | | | | | | | | | | | | | | Summary: Adds one counter to the struct counter array for counting struct array accesses. Adds instrumentation to insert counter update for struct array accesses. Reviewers: aizatsky Subscribers: llvm-commits, bruening, eugenis, kcc, zhaoqin, vitalybuka Differential Revision: http://reviews.llvm.org/D21594 llvm-svn: 274420
* [SystemZ] Move misplaced SystemZ::TDC to non-memory opcode range.Marcin Koscielnicki2016-07-022-7/+7
| | | | llvm-svn: 274417
* Add RenderScript ArchTypePirama Arumuga Nainar2016-07-022-117/+137
| | | | | | | | | | | | | | | | Summary: Add renderscript32 and renderscript64 ArchTypes. This is to configure the ABI requirement on 32-bit RenderScript that 'long' types have 64-bit size and alignment. 64-bit RenderScript is the same as AArch64, but is added here for completeness. Reviewers: echristo, rsmith Subscribers: aemerson, jfb, rampitec, dschuff, mehdi_amini, llvm-commits, srhines Differential Revision: http://reviews.llvm.org/D21333 llvm-svn: 274412
* [PM] Port ConstantHoisting to the new Pass ManagerMichael Kuperstein2016-07-027-136/+204
| | | | | | Differential Revision: http://reviews.llvm.org/D21945 llvm-svn: 274411
* [codeview] Set the Nested and Scoped ClassOptions based on the scope chainReid Kleckner2016-07-024-18/+43
| | | | | | These are set on both the declaration record and the definition record. llvm-svn: 274410
* LoadStoreVectorizer: Fix warning about extra semicolonMatt Arsenault2016-07-011-2/+2
| | | | llvm-svn: 274406
* TII: Fix inlineasm size counting comments as instsMatt Arsenault2016-07-012-7/+117
| | | | | | | The main problem was counting comments on their own line as instructions. llvm-svn: 274405
* PeepholeOptimizer: Relax assertMatt Arsenault2016-07-011-2/+4
| | | | | | Allow implicit defs llvm-svn: 274402
* [CodeView] Include the offset of nested membersDavid Majnemer2016-07-012-4/+66
| | | | | | | | | | | | | Given something like: struct S { int a; struct { int b; }; }; We would fail to give 'b' offset 4. Instead, we would give it the offset it has inside of it's struct. llvm-svn: 274400
* [CodeView] Pretty print anonymous scopesDavid Majnemer2016-07-013-16/+44
| | | | | | | | A namespace without a name should be written out as `anonymous namespace' while a tag type without a name should be written out as <unnamed-tag>. llvm-svn: 274399
* AMDGPU: Add feature for unaligned accessMatt Arsenault2016-07-017-172/+287
| | | | llvm-svn: 274398
* AMDGPU: Expand unaligned accesses earlyMatt Arsenault2016-07-016-229/+254
| | | | | | | | Due to visit order problems, in the case of an unaligned copy the legalized DAG fails to eliminate extra instructions introduced by the expansion of both unaligned parts. llvm-svn: 274397
* [msan] Fix __msan_maybe_ for non-standard type sizes.Evgeniy Stepanov2016-07-012-1/+86
| | | | | | | | | | | Fix incorrect calculation of the type size for __msan_maybe_warning_N call that resulted in an invalid (narrowing) zext instruction and "Assertion `castIsValid(op, S, Ty) && "Invalid cast!"' failed." Only happens in very large functions (with more than 3500 MSan checks) operating on integer types that are not power-of-two. llvm-svn: 274395
* AMDGPU: Improve load/store of illegal types.Matt Arsenault2016-07-0130-1454/+500
| | | | | | | | | | There was a combine before to handle the simple copy case. Split this into handling loads and stores separately. We might want to change how this handles some of the vector extloads, since this can result in large code size increases. llvm-svn: 274394
* [codeview] Don't record UDTs for anonymous structsReid Kleckner2016-07-012-53/+72
| | | | | | | | MSVC makes up names for these anonymous structs, but we don't (yet). Eventually Clang should use getTypedefNameForAnonDecl() to put some name in the debug info, and we can update the test case when that happens. llvm-svn: 274391
* IR: Set TargetPrefix for some X86 and AArch64 intrinsics where it was missingJustin Bogner2016-07-012-1/+3
| | | | llvm-svn: 274390
* Address two correctness issues in LoadStoreVectorizerAlina Sbirlea2016-07-015-6/+66
| | | | | | | | | | | | | | Summary: GetBoundryInstruction returns the last instruction as the instruction which follows or end(). Otherwise the last instruction in the boundry set is not being tested by isVectorizable(). Partially solve reordering of instructions. More extensive solution to follow. Reviewers: tstellarAMD, llvm-commits, jlebar Subscribers: escha, arsenm, mzolotukhin Differential Revision: http://reviews.llvm.org/D21934 llvm-svn: 274389
* [Hexagon] Revert r274381: that was actually wrongKrzysztof Parzyszek2016-07-011-1/+1
| | | | llvm-svn: 274384
* [Hexagon] Use MachineOperand::readsReg instead of isUseKrzysztof Parzyszek2016-07-011-1/+1
| | | | llvm-svn: 274381
* [pdb] Check the display name for <unnamed-tag>, not the linkage nameReid Kleckner2016-07-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This issue was encountered on libcmt.pdb, which has a type record that looks like this: Struct (0x1094) { TypeLeafKind: LF_STRUCTURE (0x1505) MemberCount: 3 Properties [ (0x200) HasUniqueName (0x200) ] FieldList: <field list> (0x1093) DerivedFrom: 0x0 VShape: 0x0 SizeOf: 4 Name: <unnamed-tag> LinkageName: .?AU<unnamed-tag>@@ } The checks for startswith/endswith "<unnamed-tag>" should look at the display name, not the linkage name. llvm-svn: 274376
* [codeview] Assert that our CV type records are validReid Kleckner2016-07-011-3/+27
| | | | | | | | | | | We were asserting that our type records were valid when emitting assembly, but not when emitting an object file. I've been seeing lots of LNK1285 errors (corrupt PDB) during incremental debug self-host builds with the MSVC linker, and hopefully this will catch some of them earlier. llvm-svn: 274373
* AMDGPU/SI: Enable testing several variants for si schedulerMatt Arsenault2016-07-011-2/+2
| | | | | | | | | | Enable testing different scheduling variants if sgpr usage is very high. It was previously disabled because of a bug in handleMove, but it has been fixed since. Patch by Axel Davy llvm-svn: 274372
* Specify mtriple for the frame-order.ll test.Dehao Chen2016-07-011-5/+5
| | | | | | | | | | | | Summary: original test may have different bahavior on different bot, specifically it broke llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast Reviewers: majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D21931 llvm-svn: 274368
* Revert r274347 "[ARM] Refactor Thumb2 mul instruction descs"Hans Wennborg2016-07-011-144/+327
| | | | | | This caused PR28387: Assertion "#operands for dag node doesn't match .td file!" llvm-svn: 274367
* Make extract_symbols.py be compatible with Python 3John Brawn2016-07-011-13/+21
| | | | | | | | This involved running 2to3 on it and adjusting all uses of subprocess to use universal_newlines=True so the output is text instead of binary. It remains compatible with Python 2.7. llvm-svn: 274365
* CodeGen: Use MachineInstr& in RegisterCoalescer, NFCDuncan P. N. Exon Smith2016-07-011-38/+37
| | | | | | | Remove a few more implicit iterator to pointer conversions by preferring MachineInstr&. llvm-svn: 274363
* fix documentation comments; NFCSanjay Patel2016-07-011-13/+12
| | | | llvm-svn: 274362
* CodeGen: Avoid implicit conversions in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-07-011-2/+2
| | | | | | | Avoid implicit conversions from MachineBasicBlock::iterator to MachineInstr* in TargetInstrInfo. llvm-svn: 274361
* CodeGen: Use MachineInstr& in ScheduleDAGIntrs, NFCDuncan P. N. Exon Smith2016-07-011-43/+43
| | | | | | | | | | | | | Use MachineInstr& to avoid implicit conversions from MachineBasicBlock::iterator to MachineInstr*. In one case, this could use a range-based for loop, but the other loops iterated in reverse order. One of the reverse-loops checked the MachineInstr* for nullptr, a condition that is provably unreachable. (And even if my proof has a flaw, UBSan would catch the bug.) llvm-svn: 274360
* Reapply "Define a module map entry for DebugInfo/CodeView."Adrian Prantl2016-07-012-1/+14
| | | | | | | | | This reapplies r274313 with two additional #include directives needed when submodule visibility is enabled. Fixes PR28384. llvm-svn: 274358
* Do not count debug instructions when counting number of uses to reorder ↵Dehao Chen2016-07-013-14/+138
| | | | | | | | | | | | | | frame objects. Summary: The code generation should be independent of the debug info. Reviewers: zansari, davidxl, mkuper, majnemer Subscribers: majnemer, llvm-commits Differential Revision: http://reviews.llvm.org/D21911 llvm-svn: 274357
* CodeGen: Avoid iterator conversion in UnreachableBlockElim, NFCDuncan P. N. Exon Smith2016-07-011-3/+1
| | | | | | | Avoid an unnecessary (and implicit) iterator to pointer conversion in UnreachableBlockElim by using the post-increment operator. llvm-svn: 274355
* CodeGen: Use MachineInstr& in SlotIndexes.cpp, NFCDuncan P. N. Exon Smith2016-07-011-18/+13
| | | | | | | Avoid implicit conversions from iterator to pointer by preferring MachineInstr& and using range-based for loops. llvm-svn: 274354
* CodeGen: Use MachineInstr& in RegAllocFast, NFCDuncan P. N. Exon Smith2016-07-011-31/+33
| | | | | | | | | Use MachineInstr& instead of MachineInstr* in RegAllocFast to avoid implicit conversions from MachineInstrBundleIterator. RAFast::spillAll and RAFast::spillVirtReg still take iterators, since their argument may be an end iterator from MachineBasicBlock::getFirstTerminator. llvm-svn: 274353
* [CMake] Add LLVM_BUILD_32_BITS to LLVMConfig.cmakeJohn Brawn2016-07-011-0/+2
| | | | | | | | | | | Previously out-of-tree passes could detect if LLVM was built with LLVM_BUILD_32_BITS by looking for -m32 in LLVM_DEFINITIONS, but as of r271871 it no longer appears there. Resolve this by instead emitting LLVM_BUILD_32_BITS in LLVMConfig so it can be checked for directly. Differential Revision: http://reviews.llvm.org/D21434 llvm-svn: 274351
* [ARM] Refactor Thumb2 mul instruction descsSam Parker2016-07-011-327/+144
| | | | | | | | | No functional changes. Just created wrapper classes around the 3 and 4 reg mult and mac instruction classes. Differential Revision: http://reviews.llvm.org/D21549 llvm-svn: 274347
* function_refify. NFC.Benjamin Kramer2016-07-012-10/+6
| | | | | | While there use emplace_back to create an expensive pair. llvm-svn: 274344
* Resubmit r268719 - AMDGPU/SI: Add amdgpu_kernel calling convention. Part 2.Nikolay Haustov2016-07-013-5/+71
| | | | | | | | | | | | | | | | | | | This was reverted in r268740 because of problems with corresponding Clang change. Clang change was updated and resubmitted in r274220. Check calling convention in AMDGPUMachineFunction::isKernel This will be used for AMDGPU_HSA_KERNEL symbol type in output ELF. Also, in the future unused non-kernels may be optimized. Reviewers: tstellarAMD, arsenm Subscribers: arsenm, joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D19917 llvm-svn: 274341
* [AMDGPU] Assembler: support SDWA for VOPC instructionsSam Kolton2016-07-014-45/+176
| | | | | | | | | | | | Summary: dst_sel and dst_unused disabled for VOPC as they have no effect on result Reviewers: artem.tamazov, tstellarAMD, vpykhtin Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D21376 llvm-svn: 274340
* Update libdeps; AMDGPUCodeGen requires LLVMVectorize.NAKAMURA Takumi2016-07-011-1/+1
| | | | llvm-svn: 274339
* [CodeGen] Cleanup getVectorShuffle a bit to take advantage of its new ↵Craig Topper2016-07-011-16/+16
| | | | | | ArrayRef argument and its begin/end iterators. Also use 'int' type for number of elements and loop iterators to remove several typecasts. No functional change intended. llvm-svn: 274338
* [CodeGen,Target] Remove the version of DAG.getVectorShuffle that takes a ↵Craig Topper2016-07-0110-68/+60
| | | | | | | | pointer to a mask array. Convert all callers to use the ArrayRef version. No functional change intended. For the most part this simplifies all callers. There were two places in X86 that needed an explicit makeArrayRef to shorten a statically sized array. llvm-svn: 274337
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