| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 24661
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llvm-svn: 24660
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llvm-svn: 24659
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to *return* floating point values. Don't see why myself
llvm-svn: 24658
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them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
llvm-svn: 24657
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llvm-svn: 24656
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llvm-svn: 24655
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* Added X86 dec patterns.
llvm-svn: 24654
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llvm-svn: 24653
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llvm-svn: 24652
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hopefully use patterns in the near future.
llvm-svn: 24651
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must be a pointer. This removes a type check out of the code generated by
tblgen for load matching.
llvm-svn: 24650
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the same type as the pointer type for a target.
llvm-svn: 24649
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llvm-svn: 24648
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it has more than one real use (non-chain uses).
* Record folded chain producing node in CodeGenMap.
* Do not fold a chain producing node if it has already been selected as an
operand of a chain use.
llvm-svn: 24647
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llvm-svn: 24646
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linking the entire program into one bc file.
llvm-svn: 24645
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out to me.
llvm-svn: 24644
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real use
llvm-svn: 24643
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functions can return false and causing the instruction pattern match to fail.
* Code clean up.
llvm-svn: 24642
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llvm-svn: 24641
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1. Only forward subst offsets into loads and stores, not into arbitrary
things, where it will likely become a load.
2. If the source is a cast from pointer, forward subst the cast as well,
allowing us to fold the cast away (improving cases when the cast is
from an alloca or global).
This hasn't been fully tested, but does appear to further reduce register
pressure and improve code. Lets let the testers grind on it a bit. :)
llvm-svn: 24640
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llvm-svn: 24639
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llvm-svn: 24638
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llvm-svn: 24637
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* Renamed MatchingNodes to RootNodes.
llvm-svn: 24636
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false if the match is not profitable. e.g. leal 1(%eax), %eax.
* Added patterns for X86 integer loads and LEA32.
llvm-svn: 24635
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matching code that is not currently auto-generated by tblgen, e.g. X86
addressing mode. Selection routines for complex patterns can return multiple operands, e.g. X86 addressing mode returns 4.
llvm-svn: 24634
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type when the target did not support them. Also teach Legalize how to
expand ConstantVecs.
This allows us to generate
_test:
lwz r2, 12(r3)
lwz r4, 8(r3)
lwz r5, 4(r3)
lwz r6, 0(r3)
addi r2, r2, 4
addi r4, r4, 3
addi r5, r5, 2
addi r6, r6, 1
stw r2, 12(r3)
stw r4, 8(r3)
stw r5, 4(r3)
stw r6, 0(r3)
blr
For:
void %test(%v4i *%P) {
%T = load %v4i* %P
%S = add %v4i %T, <int 1, int 2, int 3, int 4>
store %v4i %S, %v4i * %P
ret void
}
On PowerPC.
llvm-svn: 24633
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if the target supports the resultant sextinreg
llvm-svn: 24632
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llvm-svn: 24631
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when the types match up. This allows the X86 backend to compile:
sbyte %toggle_value(sbyte* %tmp.1) {
%tmp.2 = load sbyte* %tmp.1
ret sbyte %tmp.2
}
to this:
_toggle_value:
mov %EAX, DWORD PTR [%ESP + 4]
movsx %EAX, BYTE PTR [%EAX]
ret
instead of this:
_toggle_value:
mov %EAX, DWORD PTR [%ESP + 4]
movsx %EAX, BYTE PTR [%EAX]
movsx %EAX, %AL
ret
noticed in Shootout/objinst.
-Chris
llvm-svn: 24630
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llvm-svn: 24629
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llvm-svn: 24628
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llvm-svn: 24627
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the assembly side still trying to reference them by their old names. Should be safe untill we hit a language front end that lets you specify such a name.
llvm-svn: 24626
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to actually be able to use the DAG for FPcmp
llvm-svn: 24625
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llvm-svn: 24624
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llvm-svn: 24623
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llvm-svn: 24621
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llvm-svn: 24620
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PR662. Thanks to Markus for providing me with a ton of files to
reproduce the problem!
llvm-svn: 24619
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llvm-svn: 24618
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Patch by Saem Ghani, thanks!
llvm-svn: 24617
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constant nodes with vector types. Also teach the asm printer how to print
ConstantPacked constant pool entries. This allows us to generate altivec
code such as the following, which adds a vector constantto a packed float.
LCPI1_0: <4 x float> < float 0.0e+0, float 0.0e+0, float 0.0e+0, float 1.0e+0 >
.space 4
.space 4
.space 4
.long 1065353216 ; float 1
.text
.align 4
.globl _foo
_foo:
lis r2, ha16(LCPI1_0)
la r2, lo16(LCPI1_0)(r2)
li r4, 0
lvx v0, r4, r2
lvx v1, r4, r3
vaddfp v0, v1, v0
stvx v0, r4, r3
blr
For the llvm code:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = add <4 x float> %tmp1, < float 0.0, float 0.0, float 0.0, float 1.0 >
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
llvm-svn: 24616
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amount handling that PPC provides. These are generated by the lowering code
and prevents the dag combiner from assuming (rightfully) that the shifts
don't only look at 5 bits. This fixes a miscompilation of crafty with
the new front-end.
llvm-svn: 24615
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llvm-svn: 24614
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llvm-svn: 24613
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llvm-svn: 24612
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llvm-svn: 24611
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