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* Cleanup: make std::pair usage slightly less indecipherable without actually ↵Andrew Trick2011-07-211-7/+8
| | | | | | naming variables! llvm-svn: 135684
* Sink parts of TargetRegisterClass into MCRegisterClass.Benjamin Kramer2011-07-212-73/+83
| | | | llvm-svn: 135683
* ARM assembly parsing and encoding for PKHBT and PKHTB instructions.Jim Grosbach2011-07-213-0/+100
| | | | llvm-svn: 135682
* Added the infrastructute necessary for MIPS JIT support. Patch by VladimirBruno Cardoso Lopes2011-07-2112-6/+522
| | | | | | | | Stefanovic. I removed the part that actually emits the instructions cause I want that to get in better shape first and in incremental steps. This also makes it easier to review the upcoming parts. llvm-svn: 135678
* Make better use of ConstantExpr::getGetElementPtr's InBounds parameter.Jay Foad2011-07-215-31/+25
| | | | llvm-svn: 135676
* Sort case-insensitively.Jay Foad2011-07-211-3/+3
| | | | llvm-svn: 135674
* Convert ConstantExpr::getGetElementPtr andJay Foad2011-07-2120-106/+99
| | | | | | ConstantExpr::getInBoundsGetElementPtr to use ArrayRef. llvm-svn: 135673
* Update llvm-gcc-4.2 and dragonegg after converting ConstantFolder APIsJay Foad2011-07-211-0/+6
| | | | | | to use ArrayRef. llvm-svn: 135672
* Convert ConstantFolder APIs to use ArrayRef.Jay Foad2011-07-214-59/+84
| | | | llvm-svn: 135671
* move tier out of an anonymous namespace, it doesn't make senseChris Lattner2011-07-217-60/+56
| | | | | | | | to for it to be an an anon namespace and be in a header. Eliminate some extraenous uses of tie. llvm-svn: 135669
* - Register v16i16 as valid VR256 register classBruno Cardoso Lopes2011-07-213-20/+34
| | | | | | | | - Add more bitcasts for v16i16 - Since 135661 and 135662 already added the splat logic, just add one more splat test for v16i16 llvm-svn: 135663
* Add support for 256-bit versions of VPERMIL instruction. This is a newBruno Cardoso Lopes2011-07-218-0/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instruction introduced in AVX, which can operate on 128 and 256-bit vectors. It considers a 256-bit vector as two independent 128-bit lanes. It can permute any 32 or 64 elements inside a lane, and restricts the second lane to have the same permutation of the first one. With the improved splat support introduced early today, adding codegen for this instruction enable more efficient 256-bit code: Instead of: vextractf128 $0, %ymm0, %xmm0 punpcklbw %xmm0, %xmm0 punpckhbw %xmm0, %xmm0 vinsertf128 $0, %xmm0, %ymm0, %ymm1 vinsertf128 $1, %xmm0, %ymm1, %ymm0 vextractf128 $1, %ymm0, %xmm1 shufps $1, %xmm1, %xmm1 movss %xmm1, 28(%rsp) movss %xmm1, 24(%rsp) movss %xmm1, 20(%rsp) movss %xmm1, 16(%rsp) vextractf128 $0, %ymm0, %xmm0 shufps $1, %xmm0, %xmm0 movss %xmm0, 12(%rsp) movss %xmm0, 8(%rsp) movss %xmm0, 4(%rsp) movss %xmm0, (%rsp) vmovaps (%rsp), %ymm0 We get: vextractf128 $0, %ymm0, %xmm0 punpcklbw %xmm0, %xmm0 punpckhbw %xmm0, %xmm0 vinsertf128 $0, %xmm0, %ymm0, %ymm1 vinsertf128 $1, %xmm0, %ymm1, %ymm0 vpermilps $85, %ymm0, %ymm0 llvm-svn: 135662
* Improve splat promotion to handle AVX types: v32i8 and v16i16. AlsoBruno Cardoso Lopes2011-07-211-24/+87
| | | | | | | | | refactor the code and add a bunch of comments. The final shuffle emitted by handling 256-bit types is suitable for the VPERM shuffle instruction which is going to be introduced in a next commit (with a testcase which cover this commit) llvm-svn: 135661
* Add aditional patterns for vextractf128 instructionBruno Cardoso Lopes2011-07-211-0/+8
| | | | llvm-svn: 135660
* Add aditional patterns for vinsertf128 instructionBruno Cardoso Lopes2011-07-211-0/+8
| | | | llvm-svn: 135659
* Add v16i16 type to VR256 classBruno Cardoso Lopes2011-07-211-2/+2
| | | | llvm-svn: 135658
* Move code around. No functionality changesBruno Cardoso Lopes2011-07-211-65/+78
| | | | llvm-svn: 135657
* Tidy up codeBruno Cardoso Lopes2011-07-211-15/+5
| | | | llvm-svn: 135656
* LSR, correct fix for rdar://9786536. Silly casting bug.Andrew Trick2011-07-212-3/+3
| | | | llvm-svn: 135654
* LSR must sometimes sign-extend before generating double constants.Andrew Trick2011-07-212-4/+30
| | | | | | rdar://9786536 llvm-svn: 135650
* Mark instructions which are part of the frame setup with the ↵Bill Wendling2011-07-211-9/+20
| | | | | | MachineInstr::FrameSetup flag. llvm-svn: 135645
* LSR crashes on an empty IVUsers list.Andrew Trick2011-07-212-0/+27
| | | | | | rdar://9786536 llvm-svn: 135644
* X86 is the only target that uses coff format. This should fixes test ↵Evan Cheng2011-07-201-2/+3
| | | | | | failures running on Windows, Cygwin, or MingW hosts. llvm-svn: 135639
* docs/GettingStarted.html: Tweak style.NAKAMURA Takumi2011-07-201-5/+5
| | | | llvm-svn: 135637
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-2029-192/+200
| | | | | | ARM MC code from target. llvm-svn: 135636
* Remove unused function.Bill Wendling2011-07-201-64/+0
| | | | llvm-svn: 135635
* Remove the now defunct getCompactUnwindEncoding method from the frame ↵Bill Wendling2011-07-203-126/+0
| | | | | | lowering code. llvm-svn: 135634
* Refactor.Devang Patel2011-07-202-31/+42
| | | | llvm-svn: 135633
* docs/GettingStarted.html: Fix a typo and tweak a command line.NAKAMURA Takumi2011-07-201-2/+2
| | | | llvm-svn: 135632
* There are two ways to map a variable to its lexical scope. Lexical scope ↵Devang Patel2011-07-203-2/+18
| | | | | | information is embedded in MDNode describing the variable. It is also available as a part of DebugLoc attached with DBG_VALUE instruction. DebugLoc attached with an instruction is less reliable in optimized code so use information embedded in the MDNode. llvm-svn: 135629
* Clean up includes of llvm/Analysis/ConstantFolding.h so it's included where ↵Eli Friedman2011-07-205-1/+4
| | | | | | it's used and not included where it isn't. llvm-svn: 135628
* While emitting constant value, look through derived type and use underlying ↵Devang Patel2011-07-202-14/+84
| | | | | | basic type to determine size and signness of the constant value. llvm-svn: 135627
* ARM PKH shift ammount operand printing tweaks.Jim Grosbach2011-07-207-18/+41
| | | | | | | | | | Move the shift operator and special value (32 encoded as 0 for PKHTB) handling into the instruction printer. This cleans up a bit of the disassembler special casing for these instructions, more easily handles not printing the operand at all for "lsl #0" and prepares for correct asm parsing of these operands. llvm-svn: 135626
* Bring LICM into compliance with the new "Memory Model for Concurrent ↵Eli Friedman2011-07-202-18/+67
| | | | | | Operations" in LangRef. llvm-svn: 135625
* Commit LangRef changes for LLVM concurrency model. Start of supporting ↵Eli Friedman2011-07-201-0/+86
| | | | | | C++0x memory model and atomics. See thread on llvmdev titled "Reviving the new LLVM concurrency model". llvm-svn: 135624
* Unbreak the MSVC build. Since the "next" function already exists in the MSVC ↵Francois Pichet2011-07-201-3/+3
| | | | | | headers, we need the explicit llvm:: qualifier to prevent a conflict. llvm-svn: 135623
* Tidy up a bit.Jim Grosbach2011-07-203-12/+7
| | | | | | | Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename them to be a bit more descriptive that they're for the PKH instructions. llvm-svn: 135617
* ARM: Tidy up representation of PKH instruction.Jim Grosbach2011-07-205-37/+35
| | | | | | | | | The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't be also encoded as part of the shift value immediate. Otherwise we're able to represent invalid instructions, plus it needlessly complicates the representation. Preparatory work for asm parsing of these instructions. llvm-svn: 135616
* Fix cmake again :)Benjamin Kramer2011-07-201-1/+0
| | | | llvm-svn: 135613
* Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc.Evan Cheng2011-07-2028-298/+96
| | | | | | | There is still a bit more refactoring left to do in Targets. But we are now very close to fixing all the layering issues in MC. llvm-svn: 135611
* Fix cmake.Benjamin Kramer2011-07-201-0/+1
| | | | llvm-svn: 135609
* Sketch out an CFG reconstruction mode for llvm-objdump.Benjamin Kramer2011-07-203-3/+242
| | | | | | | | | | | | | - Not great yet, but it's a start. - Requires an object file with a symbol table. (I really want to fix this, but it'll need a whole new algorithm) - ELF and COFF won't work at the moment due to libObject shortcomings. To try it out run $ llvm-objdump -d --cfg foo.o This will create a graphviz file for every symbol in the object file's text section containing a CFG. llvm-svn: 135608
* Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389.Eli Friedman2011-07-202-3/+6
| | | | llvm-svn: 135607
* Add parsing/encoding tests for ARM ORR instruction.Jim Grosbach2011-07-202-6/+79
| | | | llvm-svn: 135602
* Consolidate ARM NOP encoding test.Jim Grosbach2011-07-202-11/+9
| | | | llvm-svn: 135600
* ARM parsing and encoding tests for MVNJim Grosbach2011-07-201-0/+57
| | | | llvm-svn: 135599
* ARM assembly parsing of MUL instruction.Jim Grosbach2011-07-202-1/+16
| | | | | | | Correctly handle 's' bit and predication suffices. Add parsing and encoding tests. llvm-svn: 135596
* PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS.Eli Friedman2011-07-202-5/+13
| | | | llvm-svn: 135595
* Initialize the EHFrameSection pointer to zero.Benjamin Kramer2011-07-201-0/+1
| | | | | | This should fix the spurious buildbot errors. llvm-svn: 135594
* Regenerate configure and friends for Chad.Eric Christopher2011-07-202-2/+21
| | | | llvm-svn: 135592
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