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* Teach the interpreter to handle vector compares and additional vector ↵Nadav Rotem2013-04-266-44/+453
| | | | | | | | arithmetic operations. Patch by Yuri Veselov. llvm-svn: 180626
* Use llvm/Object/MachO.h in macho-dumper. Drop the old macho parser.Rafael Espindola2013-04-269-976/+347
| | | | | | | | | | | | | | | | | | | | | For Mach-O there were 2 implementations for parsing object files. A standalone llvm/Object/MachOObject.h and llvm/Object/MachO.h which implements the generic interface in llvm/Object/ObjectFile.h. This patch adds the missing features to MachO.h, moves macho-dump to use MachO.h and removes ObjectFile.h. In addition to making sure that check-all is clean, I checked that the new version produces exactly the same output in all Mach-O files in a llvm+clang build directory (including executables and shared libraries). To test the performance, I ran macho-dump over all the files in a llvm+clang build directory again, but this time redirecting the output to /dev/null. Both the old and new versions take about 4.6 seconds (2.5 user) to finish. llvm-svn: 180624
* The exception demo needs its symbols exported.Rafael Espindola2013-04-261-0/+2
| | | | llvm-svn: 180622
* R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTETom Stellard2013-04-262-1/+5
| | | | | | | | | We need to intialize this to something and since clang does not set the shader type attribute and clang is used only for compute shaders, initializing it to COMPUTE seems like the best choice. Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 180620
* cleanup testcase some moreAdrian Prantl2013-04-261-11/+11
| | | | | | rdar://problem/13056109 llvm-svn: 180619
* fix a typo that due to cu&paste quadrupled itselfAdrian Prantl2013-04-262-4/+4
| | | | | | rdar://problem/13056109 llvm-svn: 180618
* ARM: Fix encoding of hint instruction for Thumb.Quentin Colombet2013-04-2610-22/+59
| | | | | | | | | | | | | | | "hint" space for Thumb actually overlaps the encoding space of the CPS instruction. In actuality, hints can be defined as CPS instructions where imod and M bits are all nil. Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe, sev) in DecodeT2CPSInstruction. This commit adds a proper diagnostic message for Imm0_4 and updates all tests. Patch by Mihail Popa <Mihail.Popa@arm.com>. llvm-svn: 180617
* Add missing ':'.Rafael Espindola2013-04-261-1/+1
| | | | llvm-svn: 180616
* Bugfix for the debug intrinsic handling in InstCombiner:Adrian Prantl2013-04-263-4/+129
| | | | | | | | | | | Since we can't guarantee that the original dbg.declare instrinsic is removed by LowerDbgDeclare(), we need to make sure that we are not inserting the same dbg.value intrinsic over and over. This removes tons of redundant DIEs when compiling optimized code. rdar://problem/13056109 llvm-svn: 180615
* PowerPC: Use RegisterOperand instead of RegisterClass operandsUlrich Weigand2013-04-263-432/+452
| | | | | | | | | | | | | | | | | In the default PowerPC assembler syntax, registers are specified simply by number, so they cannot be distinguished from immediate values (without looking at the opcode). This means that the default operand matching logic for the asm parser does not work, and we need to specify custom matchers. Since those can only be specified with RegisterOperand classes and not directly on the RegisterClass, all instructions patterns used by the asm parser need to use a RegisterOperand (instead of a RegisterClass) for all their register operands. This patch adds one RegisterOperand for each RegisterClass, using the same name as the class, just in lower case, and updates all instruction patterns to use RegisterOperand instead of RegisterClass operands. llvm-svn: 180611
* Re-write the address propagation code for pre-indexed loads/stores to take ↵Silviu Baranga2013-04-261-14/+29
| | | | | | into account some previously misssed cases (PRE_DEC addressing mode, the offset and base address are swapped, etc). This should fix PR15581. llvm-svn: 180609
* PowerPC: Fix encoding of vsubcuw and vsum4sbs instructionsUlrich Weigand2013-04-261-2/+2
| | | | | | | | | When testing the asm parser, I noticed wrong encodings for the above instructions (wrong sub-opcodes). Tests will be added together with the asm parser. llvm-svn: 180608
* PowerPC: Fix encoding of stfsu and stfdu instructionsUlrich Weigand2013-04-261-2/+2
| | | | | | | | | | | When testing the asm parser, I noticed wrong encodings for the above instructions (wrong sub-opcodes). Note that apparently the compiler currently never generates pre-inc instructions for floating point types for some reason ... Tests will be added together with the asm parser. llvm-svn: 180607
* PowerPC: Fix encoding of rldimi and rldcl instructionsUlrich Weigand2013-04-263-3/+36
| | | | | | | | | | When testing the asm parser, I noticed wrong encodings for the above instructions (wrong operand name in rldimi, wrong form and sub-opcode for rldcl). Tests will be added together with the asm parser. llvm-svn: 180606
* PowerPC: Support PC-relative fixup_ppc_brcond14.Ulrich Weigand2013-04-261-0/+3
| | | | | | | | When testing the asm parser, I ran into an error when using a conditional branch to an external symbol (this doesn't occur in compiler-generated code) due to missing support in PPCELFObjectWriter::getRelocTypeInner. llvm-svn: 180605
* ARM/NEON: Pattern match vector integer abs to vabs.Benjamin Kramer2013-04-262-0/+114
| | | | llvm-svn: 180604
* X86: Now that we have a canonical form for vector integer abs, match it into ↵Benjamin Kramer2013-04-262-13/+181
| | | | | | pabs. llvm-svn: 180600
* DAGCombiner: Canonicalize vector integer abs in the same way we do it for ↵Benjamin Kramer2013-04-262-0/+108
| | | | | | | | | | scalars. This already helps SSE2 x86 a lot because it lacks an efficient way to represent a vector select. The long term goal is to enable the backend to match a canonicalized pattern into a single instruction (e.g. vabs or pabs). llvm-svn: 180597
* LoopVectorizer: Calculate the number of pointers to disambiguate at runtime ↵Nadav Rotem2013-04-262-4/+95
| | | | | | based on the numbers of reads and writes. llvm-svn: 180593
* Use 'git svn find-rev' in git-svnrevert instead of shell script fu.Michael Gottesman2013-04-261-4/+3
| | | | | | Thanks Chandler! llvm-svn: 180592
* Revert "[objc-arc] Added ImpreciseAutoreleaseSet to track autorelease calls ↵Michael Gottesman2013-04-261-38/+0
| | | | | | | | | | | | | | that were once autoreleaseRV instructions." This reverts commit r180222. I think this might tie in with a different problem which will require a different approach potentially. I am reverting this in the case I need to go down that second path. My apologies for the noise. = /. llvm-svn: 180590
* Updated GettingStarted.rst so that it references utils/git-svn for git-svnup ↵Michael Gottesman2013-04-261-26/+11
| | | | | | instead of catting it into the documentation itself. llvm-svn: 180589
* Added the scripts git-svnup/git-svnrevert to utils/git-svn.Michael Gottesman2013-04-262-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | | It makes more sense to have git-svnup here than catting said file in the documentation (where we should rather point users to this directory). I included git-svnrevert as an additional gift to the community. I will update the documentation in a second commit later today. git-svnrevert takes in a git hash for a commit, looks up the svn revision for said commit and then creates the normal git revert commit message with the one liner message, except instead of saying Revert "<<<INSERT ONELINER HERE>>>" This reverts commit <<<INSERT GITHASH HERE>>> It says: Revert "<<<INSERT ONELINER HERE>>>" This reverts commit r<<<INSERT SVN REVISION HERE>>> so git hashes will not escape into our svn logs (which just look unseemly). llvm-svn: 180587
* Mips assembler: .set reorder supportJack Carter2013-04-252-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | Mips have delayslots for certain instructions like jumps and branches. These are instructions that follow the branch or jump and are executed before the jump or branch is completed. Early Mips compilers could not cope with delayslots and left them up to the assembler. The assembler would fill the delayslots with the appropriate instruction, usually just a nop to allow correct runtime behavior. The default behavior for this is set with .set reorder. To tell the assembler that you don't want it to mess with the delayslot one used .set noreorder. For backwards compatibility we need to support .set reorder and have it be the default behavior in the assembler. Our support for it is to insert a NOP directly after an instruction with a delayslot when in .set reorder mode. Contributer: Vladimir Medic llvm-svn: 180584
* Remove SMLoc paired with CHECK-NOT patterns. Not functionality change.Michael Liao2013-04-252-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | Pattern has source location by itself. After adding a trivial method to retrieve it, it's unnecessary to pair a source location for CHECK-NOT patterns. One thing revised after this is the diagnostic info is more accurate by pointing to the start of the CHECK-NOT pattern instead of the end of the CHECK-NOT pattern. E.g. diagnostic message previously looks like <stdin>:1:1: error: CHECK-NOT: string occurred! test ^ test.txt:1:16: note: CHECK-NOT: pattern specified here CHECK-NOT: test ^ is changed to <stdin>:1:1: error: CHECK-NOT: string occurred! test ^ test.txt:1:12: note: CHECK-NOT: pattern specified here CHECK-NOT: test ^ llvm-svn: 180578
* Make function documentation conform to llvm standards.Preston Gurd2013-04-251-30/+32
| | | | | | Expunge all remaining traces and use of live variable information. llvm-svn: 180577
* ARM cost model: Integer div and rem is lowered to a function callArnold Schwaighofer2013-04-252-0/+518
| | | | | | | | Reflect this in the cost model. I observed this in MiBench/consumer-lame. radar://13354716 llvm-svn: 180576
* Re-enabling MCJIT object caching with memory leak fixedAndrew Kaylor2013-04-256-18/+370
| | | | llvm-svn: 180575
* revert r179735, it has no testcases, and doesn't really make sense.Chris Lattner2013-04-254-34/+29
| | | | llvm-svn: 180574
* This patch adds the X86FixupLEAs pass, which will reduce instructionPreston Gurd2013-04-2511-1/+444
| | | | | | | | latency for certain models of the Intel Atom family, by converting instructions into their equivalent LEA instructions, when it is both useful and possible to do so. llvm-svn: 180573
* LoopVectorizer: No need to generate pointer disambiguation checks between ↵Nadav Rotem2013-04-252-4/+48
| | | | | | readonly pointers. llvm-svn: 180570
* [mc-coff] Forward Linker Option flags into the .drectve sectionReid Kleckner2013-04-253-0/+73
| | | | | | | | | | | | | | Summary: This is modelled on the Mach-O linker options implementation and should support a Clang implementation of #pragma comment(lib/linker). Reviewers: rafael CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D724 llvm-svn: 180569
* Fix section relocation for SECTIONREL32 with immediate offset.Rafael Espindola2013-04-253-2/+36
| | | | | | Patch by Kai Nacke. This matches the gnu as output. llvm-svn: 180568
* Remove tailing whitespacesMichael Liao2013-04-251-1/+1
| | | | llvm-svn: 180564
* [inline asm] Add a test case for r180226. The specific issue is that the inlineChad Rosier2013-04-251-0/+9
| | | | | | | assembly is requesting a 64-bit register, which is invalid for i386. rdar://13731657 llvm-svn: 180445
* Use a pointer as the relocation iterator.Rafael Espindola2013-04-251-24/+29
| | | | | | | | Since the relocation iterator walks only the relocations in one section, we can just use a pointer and avoid fetching information about the section at every reference. llvm-svn: 180262
* Clarify getRelocationAddress x getRelocationOffset a bit.Rafael Espindola2013-04-2511-58/+54
| | | | | | | | | | getRelocationAddress is for dynamic libraries and executables, getRelocationOffset for relocatable objects. Mark the getRelocationAddress of COFF and MachO as not implemented yet. Add a test of ELF's. llvm-readobj -r now prints the same values as readelf -r. llvm-svn: 180259
* Fix constant folding for one lane vector types. Constant folding one lane ↵Silviu Baranga2013-04-252-1/+19
| | | | | | vector types not returns a vector instead of a scalar. llvm-svn: 180254
* Revert "Adding object caching support to MCJIT"Rafael Espindola2013-04-256-367/+18
| | | | | | | | | | This reverts commit 07f03923137a91e3cca5d7fc075a22f8c9baf33a. Looks like it broke the valgrind bot: http://lab.llvm.org:8011/builders/llvm-x86_64-linux-vg_leak/builds/649 llvm-svn: 180249
* Revert "Exposing MCJIT through C API"Rafael Espindola2013-04-256-249/+48
| | | | | | | | | | This reverts commit 8c31b298149ca3c3f2bbd9e8aa9a01c4d91f3d74. It looks like this commit broke some bots: http://lab.llvm.org:8011/builders/llvm-ppc64-linux2/builds/5209 llvm-svn: 180248
* Don't compute a std::vector<uint8_t> just to write it out a stream.Rafael Espindola2013-04-251-83/+17
| | | | llvm-svn: 180247
* Test case for r180241.Akira Hatanaka2013-04-251-0/+22
| | | | llvm-svn: 180246
* Test case for r180238.Akira Hatanaka2013-04-251-0/+22
| | | | llvm-svn: 180245
* [mips] Add definitions of micromips load and store instructions.Akira Hatanaka2013-04-254-17/+43
| | | | | | Patch by Zoran Jovanovic. llvm-svn: 180241
* Allow users to choose identity used to sign tools.Filipe Cabecinhas2013-04-251-1/+3
| | | | | | | | | | | Summary: No change if the identity isn't defined by the makefile. Reviewers: echristo Differential Revision: http://llvm-reviews.chandlerc.com/D632 llvm-svn: 180240
* [mips] Add definitions of micromips shift instructions.Akira Hatanaka2013-04-254-12/+62
| | | | | | Patch by Zoran Jovanovic. llvm-svn: 180238
* Fixing OCAML bindings for MCJITAndrew Kaylor2013-04-251-1/+1
| | | | llvm-svn: 180232
* R600: Initialize BooleanVectorContentsTom Stellard2013-04-241-0/+1
| | | | | | Fixes test/CodeGen/R600/setcc.ll llvm-svn: 180231
* R600: Use SHT_PROGBITS for the .AMDGPU.config sectionTom Stellard2013-04-242-1/+2
| | | | | | | | The libelf implementation that is distributed here: http://www.mr511.de/software/english.html will not parse sections that are marked SHT_NULL. llvm-svn: 180230
* Exposing MCJIT through C APIAndrew Kaylor2013-04-246-48/+249
| | | | | | Patch by Filip Pizlo llvm-svn: 180229
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