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* InferAddressSpaces: Remove redundant assertMatt Arsenault2017-04-241-1/+0
| | | | | | | This is just asserting all the operations are handled in the switch, which the unreachable already handles. llvm-svn: 301270
* [ARM, x86] add more vector tests for bool math; NFCSanjay Patel2017-04-242-0/+64
| | | | | | | | I'm proposing a fold for increment-of-sexted-bool in: https://reviews.llvm.org/D31944 ...so we need to know what happens in more cases like these. llvm-svn: 301269
* [git-llvm] Remove CR from middle of svn propget outputReid Kleckner2017-04-241-0/+2
| | | | llvm-svn: 301268
* Make getSlotAttributes return an AttributeSet instead of a wrapper listReid Kleckner2017-04-245-34/+20
| | | | | | | | Remove the temporary, poorly named getSlotSet method which did the same thing. Also remove getSlotNode, which is a hold-over from when we were dealing with AttributeSetNode* instead of AttributeSet. llvm-svn: 301267
* [git-llvm] Make `push` work on CRLF files with svn:eol-style=nativeReid Kleckner2017-04-241-7/+60
| | | | | | | | | | | | | | | | | | | | | | Summary: `git apply` on Windows doesn't work for files that SVN checks out as CRLF. There is no way to force SVN to check everything out with Unix line endings on Windows. Files with svn:eol-style=native will always come out with CRLF, breaking `git apply`, which wants Unix line endings. My workaround is to list all files with this property set in the change, and run `dos2unix` on them. SVN doesn't commit a massive line ending change because the svn:eol-style property indicates that these are text files. Tested on r301245. Reviewers: zturner, jlebar Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32452 llvm-svn: 301262
* [InstSimplify] use ConstantRange to simplify more and-of-icmpsSanjay Patel2017-04-245-302/+95
| | | | | | | | | | | | | We can simplify (and (icmp X, C1), (icmp X, C2)) to one of the icmps in many cases. I had to check some of these with Alive to prove to myself it's right, but everything seems to check out. Eg, the code in instcombine was completely ignoring predicates with mismatched signedness. Handling or-of-icmps would be a follow-up step. Differential Revision: https://reviews.llvm.org/D32143 llvm-svn: 301260
* [DAGCombiner] Use APInt::intersects to avoid tmp variable. NFCI.Simon Pilgrim2017-04-241-1/+3
| | | | llvm-svn: 301258
* AMDGPU: Slightly simplify prolog reserved register handlingMatt Arsenault2017-04-241-25/+27
| | | | | | | | | | | | | | Rely on MachineRegisterInfo's knowledge of used physical registers. Move flat_scratch initialization earlier, so the uses are visible when making these decisions. This will make it easier to add another reserved register at the end for the stack pointer rather than handling another special case. llvm-svn: 301254
* Cosmetic change.Galina Kistanova2017-04-241-0/+1
| | | | llvm-svn: 301253
* ProfileData: clean up some stale declarations (NFC)Saleem Abdulrasool2017-04-241-8/+0
| | | | | | These were removed in SVN r300381. Remove the declarations. llvm-svn: 301252
* Small addition on how to add a builder.Galina Kistanova2017-04-241-0/+1
| | | | llvm-svn: 301248
* [AMDGPU][mc][tests][NFC] Bulk ISA tests: update for Gfx7/Gfx8, add for Gfx9.Artem Tamazov2017-04-244-58050/+128900
| | | | llvm-svn: 301247
* [Bitcode] Refactor attribute group writing to avoid getSlotAttributesReid Kleckner2017-04-245-56/+67
| | | | | | | | | | | | | | | | | Summary: That API creates a temporary AttributeList to carry an index and a single AttributeSet. We need to carry the index in addition to the set, because that is how attribute groups are currently encoded. NFC Reviewers: pcc Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32262 llvm-svn: 301245
* Update profile during memory instrinsic optimizationTeresa Johnson2017-04-242-6/+19
| | | | | | | | | | | | | | | | Summary: Ensure that the new merge BB (which contains the rest of the original BB after the mem op being optimized) gets a profile frequency, in case there are additional mem ops later in the BB. Otherwise they get skipped as the merge BB looks cold. Reviewers: davidxl, xur Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32447 llvm-svn: 301244
* Revert "StructurizeCFG: Directly invert cmp instructions"Matt Arsenault2017-04-248-184/+112
| | | | | | | | This reverts commit r300732. This breaks a few tests. I think the problem is related to adding more uses of the condition that don't yet exist at this point. llvm-svn: 301242
* [LoopUnroll] Remove spurious newline.Davide Italiano2017-04-241-1/+0
| | | | | | | Eli pointed out in the review, but I didn't squash the two commits correctly. Pointy-hat to me. llvm-svn: 301241
* Revert "Refactor DynamicLibrary so searching for a symbol will have a ↵Frederich Munch2017-04-2411-576/+285
| | | | | | | | | | defined order" The i686-mingw32-RA-on-linux bot is still having errors. This reverts commit r301236. llvm-svn: 301240
* [LoopUnroll] Don't try to unroll non canonical loops.Davide Italiano2017-04-242-0/+41
| | | | | | | | | | | | The current Loop Unroll implementation works with loops having a single latch that contains a conditional branch to a block outside the loop (the other successor is, by defition of latch, the header). If this precondition doesn't hold, avoid unrolling the loop as the code is not ready to handle such circumstances. Differential Revision: https://reviews.llvm.org/D32261 llvm-svn: 301239
* [LIR] Obey non-integral pointer semanticsSanjoy Das2017-04-242-0/+53
| | | | | | | | | | | | | | Summary: See http://llvm.org/docs/LangRef.html#non-integral-pointer-type Reviewers: haicheng Reviewed By: haicheng Subscribers: mcrosier, mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D32196 llvm-svn: 301238
* Avoid unnecessary copies in some for loopsSaleem Abdulrasool2017-04-243-6/+6
| | | | | | | | Use constant references rather than `const auto` which will cause the copy constructor. These particular cases cause issues for the swift compiler. llvm-svn: 301237
* Refactor DynamicLibrary so searching for a symbol will have a defined order andFrederich Munch2017-04-2411-285/+576
| | | | | | | | | | | | | | | | | | | | | | | | | | | libraries are properly unloaded when llvm_shutdown is called. Summary: This was mostly affecting usage of the JIT, where storing the library handles in a set made iteration unordered/undefined. This lead to disagreement between the JIT and native code as to what the address and implementation of particularly on Windows with stdlib functions: JIT: putenv_s("TEST", "VALUE") // called msvcrt.dll, putenv_s JIT: getenv("TEST") -> "VALUE" // called msvcrt.dll, getenv Native: getenv("TEST") -> NULL // called ucrt.dll, getenv Also fixed is the issue of DynamicLibrary::getPermanentLibrary(0,0) on Windows not giving priority to the process' symbols as it did on Unix. Reviewers: chapuni, v.g.vassilev, lhames Reviewed By: lhames Subscribers: danalbert, srhines, mgorny, vsk, llvm-commits Differential Revision: https://reviews.llvm.org/D30107 llvm-svn: 301236
* Move value type list from TargetRegisterClass to TargetRegisterInfoKrzysztof Parzyszek2017-04-2416-70/+85
| | | | | | Differential Revision: https://reviews.llvm.org/D31937 llvm-svn: 301234
* Revert r301231: Accidentally committed stale filesKrzysztof Parzyszek2017-04-2416-77/+68
| | | | | | I forgot to commit local changes before commit. llvm-svn: 301232
* Move value type list from TargetRegisterClass to TargetRegisterInfoKrzysztof Parzyszek2017-04-2416-68/+77
| | | | | | Differential Revision: https://reviews.llvm.org/D31937 llvm-svn: 301231
* AMDGPU: Select scratch mubuf offsets when pointer is a constantMatt Arsenault2017-04-245-47/+242
| | | | | | | | In call sequence setups, there may not be a frame index base and the pointer is a constant offset from the frame pointer / scratch wave offset register. llvm-svn: 301230
* AMDGPU: Set StackGrowsUp in MCAsmInfoMatt Arsenault2017-04-241-0/+1
| | | | | | Not sure what this does though. llvm-svn: 301229
* [AMDGPU] Merge M0 initializationsStanislav Mekhanoshin2017-04-244-19/+323
| | | | | | | | | | Merges equivalent initializations of M0 and hoists them into a common dominator block. Technically the same code can be used with any register, physical or virtual. Differential Revision: https://reviews.llvm.org/D32279 llvm-svn: 301228
* Handle invariant.group.barrier in BasicAAPiotr Padlewski2017-04-245-13/+56
| | | | | | | | | | | | | | | | | | | | | Summary: llvm.invariant.group.barrier returns pointer that mustalias pointer it takes. It can't be marked with `returned` attribute, because it would be remove easily. The other reason is that only Alias Analysis can know about this, because if any other pass would know it, then the result would be replaced with it's argument, which would be invalid. We can think about returned pointer as something that mustalias, but it doesn't have to be bitwise the same as the argument. Reviewers: dberlin, chandlerc, hfinkel, sanjoy Subscribers: reames, nlewycky, rsmith, anna, amharc Differential Revision: https://reviews.llvm.org/D31585 llvm-svn: 301227
* [asan] Let the frontend disable gc-sections optimization for asan globals.Evgeniy Stepanov2017-04-243-17/+86
| | | | | | Also extend -asan-globals-live-support flag to all binary formats. llvm-svn: 301226
* [SimplifyCFG] Fix for non-determinism in codegenMandeep Singh Grang2017-04-241-1/+1
| | | | | | | | | | | | | | Summary: This patch fixes issues in codegen uncovered due to https://reviews.llvm.org/D26718 Reviewers: majnemer, chenli, davide Reviewed By: davide Subscribers: davide, arsenm, llvm-commits Differential Revision: https://reviews.llvm.org/D26726 llvm-svn: 301222
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-2447-232/+296
| | | | | | | | | | | | | | | 1. RegisterClass::getSize() is split into two functions: - TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC) const; - TargetRegisterInfo::getSpillSize(const TargetRegisterClass &RC) const; 2. RegisterClass::getAlignment() is replaced by: - TargetRegisterInfo::getSpillAlignment(const TargetRegisterClass &RC) const; This will allow making those values depend on subtarget features in the future. Differential Revision: https://reviews.llvm.org/D31783 llvm-svn: 301221
* Don't test setting sticky bits on files for modern BSDsDimitry Andric2017-04-241-0/+7
| | | | | | | | | | | | | | | | | | | Summary: In rL297945, jhenderson added methods for setting permissions to sys::fs, but some of the unittests that attempt to set sticky bits (01000) on files fail on modern BSDs, such as FreeBSD, NetBSD and OpenBSD. This is because those systems do not allow regular users to set sticky bits on files, only on directories. Fix it by disabling these particular tests on modern BSDs. Reviewers: emaste, brad, jhenderson Reviewed By: jhenderson Subscribers: joerg, krytarowski, llvm-commits Differential Revision: https://reviews.llvm.org/D32120 llvm-svn: 301220
* Don't emit CFI instructions at the end of a functionAdrian Prantl2017-04-245-21/+24
| | | | | | | | | | | | | | | | | | | | | | | | | When functions are terminated by unreachable instructions, the last instruction might trigger a CFI instruction to be generated. However, emitting it would be be illegal since the function (and thus the FDE the CFI is in) has already ended with the previous instruction. Darwin's dwarfdump --verify --eh-frame complains about this and the specification supports this. Relevant bits from the DWARF 5 standard (6.4 Call Frame Information): "[The] address_range [field in an FDE]: The number of bytes of program instructions described by this entry." "Row creation instructions: [...] The new location value is always greater than the current one." The first quotation implies that a CFI cannot describe a target address outside of the enclosing FDE's range. rdar://problem/26244988 Differential Revision: https://reviews.llvm.org/D32246 llvm-svn: 301219
* Updates documentation for a syntax sugar libfuzzer flag,George Karpenkov2017-04-241-3/+9
| | | | | | as implemented in https://reviews.llvm.org/D32193 llvm-svn: 301217
* CodeGen: Add a hook for getFenceOperandTyYaxun Liu2017-04-245-2/+33
| | | | | | | | | | | | | | Currently the operand type for ATOMIC_FENCE assumes value type of a pointer in address space 0. This is fine for most targets. However for amdgcn target, the size of pointer in address space 0 depends on triple environment. For amdgiz environment, it is 64 bit but for other environment it is 32 bit. On the other hand, amdgcn target expects 32 bit fence operands independent of the target triple environment. Therefore a hook is need in target lowering for getting the fence operand type. This patch has no effect on targets other than amdgcn. Differential Revision: https://reviews.llvm.org/D32186 llvm-svn: 301215
* Revert "Compute safety information in a much finer granularity."Evgeniy Stepanov2017-04-246-105/+55
| | | | | | Use-after-free in llvm::isGuaranteedToExecute. llvm-svn: 301214
* [InstSimplify] move (A & ~B) | (A ^ B) -> (A ^ B) from InstCombineSanjay Patel2017-04-244-66/+66
| | | | | | | | | | | This is a straight cut and paste, but there's a bigger problem: if this fold exists for simplifyOr, there should be a DeMorganized version for simplifyAnd. But more than that, we have a patchwork of ad hoc logic optimizations in InstCombine. There should be some structure to ensure that we're not missing sibling folds across and/or/xor. llvm-svn: 301213
* X86RegisterInfo: eliminateFrameIndex: Avoid code duplication; NFCMatthias Braun2017-04-243-34/+24
| | | | | | | | | | | | | | | | | Re-Commit of r300922 and r300923 with less aggressive assert (see discussion at the end of https://reviews.llvm.org/D32205) X86RegisterInfo::eliminateFrameIndex() and X86FrameLowering::getFrameIndexReference() both had logic to compute the base register. This consolidates the code. Also use MachineInstr::isReturn instead of manually enumerating tail call instructions (return instructions were not included in the previous list because they never reference frame indexes). Differential Revision: https://reviews.llvm.org/D32206 llvm-svn: 301211
* Use DW_OP_stack_value when reconstructing variable values with arithmetic.Adrian Prantl2017-04-242-20/+67
| | | | | | | | | | | | | | | When the location description of a source variable involves arithmetic on the value itself, it needs to be marked with DW_OP_stack_value since it is not describing the variable's location, but rather its value. This is a follow-up to r297971 and fixes the source testcase quoted in the comment in debuginfo-dce.ll. rdar://problem/30725338 This reapplies r301093 without modifications. llvm-svn: 301210
* Add a testcase for DIExpression(DW_OP_stack_value)Adrian Prantl2017-04-243-1/+125
| | | | | | | | and relax the assertion that prohibited its emission. This fixes the assertion failure uncovered by r301093. llvm-svn: 301209
* AMDGPU: Add StackPtr and FramePtr registers to MFIMatt Arsenault2017-04-242-0/+26
| | | | | | These will be necessary for setting up call sequences. llvm-svn: 301208
* AMDGPU: Move trap lowering to DAGMatt Arsenault2017-04-247-62/+89
| | | | | | | | | | | Fixes traps in any block besides the entry block, and fixes depending on a live-in physical register by using a virtual register copy. Also happens to stop emitting a nop in the case debug trap is not supported. llvm-svn: 301206
* [DomPrinter] Add a way to programmatically dump a dot representation.Davide Italiano2017-04-242-0/+20
| | | | | | Differential Revision: https://reviews.llvm.org/D32145 llvm-svn: 301205
* [llvm-pdbdump] Merge functionality of graphical and text dumpers.Zachary Turner2017-04-2414-212/+111
| | | | | | | | | | | | | | The *real* difference between these two was that a) The "graphical" dumper could recurse, while the text one could not. b) The "text" dumper could display nested types and functions, while the graphical one could not. Merge these two so that there is only one dumper that can recurse arbitrarily deep and optionally display nested types or not. llvm-svn: 301204
* [llvm-pdbdump] Re-write the record layout code to be more resilient.Zachary Turner2017-04-2425-450/+451
| | | | | | | | This reworks the way virtual bases are handled, and also the way padding is detected across multiple levels of aggregates, producing a much more accurate result. llvm-svn: 301203
* [APInt] Simplify the zext and sext methodsCraig Topper2017-04-241-33/+18
| | | | | | | | | | This replaces a hand written copy loop with a call to memcpy for both zext and sext. For sext, it replaces multiple if/else blocks propagating sign information forward. Now we just do a copy, a sign extension on the last copied word, a memset, and clearUnusedBits. Differential Revision: https://reviews.llvm.org/D32417 llvm-svn: 301201
* Testing commit credentialsGeorge Karpenkov2017-04-241-0/+1
| | | | llvm-svn: 301200
* InstCombine: Fix assert when reassociating fsub with undefMatt Arsenault2017-04-242-0/+49
| | | | | | | | | | | | | There is logic to track the expected number of instructions produced. It thought in this case an instruction would be necessary to negate the result, but here it folded into a ConstantExpr fneg when the non-undef value operand was cancelled out by the second fsub. I'm not sure why we don't fold constant FP ops with undef currently, but I think that would also avoid this problem. llvm-svn: 301199
* [APInt] Add ashrInPlace method and rewrite ashr to make a copy and then call ↵Craig Topper2017-04-244-79/+104
| | | | | | | | | | | | ashrInPlace. This patch adds an in place version of ashr to match lshr and shl which were recently added. I've tried to make this similar to the lshr code with additions to handle the sign extension. I've also tried to do this with less if checks than the current ashr code by sign extending the original result to a word boundary before doing any of the shifting. This removes a lot of the complexity of determining where to fill in sign bits after the shifting. Differential Revision: https://reviews.llvm.org/D32415 llvm-svn: 301198
* AMDGPU: Move v_readlane lane select from VGPR to SGPRNicolai Haehnle2017-04-243-0/+32
| | | | | | | | | | | | | | | | | Summary: Fix a compiler bug when the lane select happens to end up in a VGPR. Clarify the semantic of the corresponding intrinsic to be that of the corresponding GLSL: the lane select must be uniform across a wave front, otherwise results are undefined. Reviewers: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D32343 llvm-svn: 301197
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