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* Add skeleton for the pre-register allocation live interval splitting pass.Evan Cheng2008-10-202-0/+83
| | | | llvm-svn: 57847
* Update the stub and callback code to handle lazy compilation. The stubJim Grosbach2008-10-204-64/+128
| | | | | | | | | | is re-written by the callback to branch directly to the compiled code in future invocations. Added back in range-based memory permission functions for the updating of the stub on Darwin. llvm-svn: 57846
* Fast-isel no longer an experiment.Dan Gohman2008-10-201-1/+1
| | | | llvm-svn: 57845
* Add a register class -> virtual registers map.Evan Cheng2008-10-202-7/+31
| | | | llvm-svn: 57844
* This forward declaration is unnecessary.Evan Cheng2008-10-201-1/+0
| | | | llvm-svn: 57843
* Support operations like fp_to_uint with a vectorDuncan Sands2008-10-202-1/+53
| | | | | | | | | result type when the result type is legal but not the operand type. Add additional support for EXTRACT_SUBVECTOR and CONCAT_VECTORS, needed to handle such cases. llvm-svn: 57840
* Teach getTypeToTransformTo to return somethingDuncan Sands2008-10-201-4/+5
| | | | | | | | sensible for vectors being scalarized. Note that this method can't return anything very sensible when splitting non-power-of-two vectors. llvm-svn: 57839
* LegalizeTypes support for atomic operation promotion.Duncan Sands2008-10-202-3/+78
| | | | llvm-svn: 57838
* Use DAG.getIntPtrConstant rather than DAG.getConstantDuncan Sands2008-10-202-6/+4
| | | | | | with TLI.getPointerTy for a small simplification. llvm-svn: 57837
* Always use either MVT::i1 or getSetCCResultType forDuncan Sands2008-10-201-15/+51
| | | | | | | | the condition of a SELECT node. Make sure that the correct extension type (any-, sign- or zero-extend) is used. llvm-svn: 57836
* Formatting - no functional change.Duncan Sands2008-10-202-7/+6
| | | | llvm-svn: 57834
* Don't use a random type for the select condition,Duncan Sands2008-10-201-2/+1
| | | | | | use an MVT::i1 and simplify the code while there. llvm-svn: 57833
* Fix a typo in a comment.Dan Gohman2008-10-201-1/+1
| | | | llvm-svn: 57832
* Have X86 custom lowering for LegalizeTypes useDuncan Sands2008-10-201-10/+12
| | | | | | | | | | | | | LowerOperation if it doesn't know what else to do. This methods should probably be factorized some, but this is good enough for the moment. Have LowerATOMIC_BINARY_64 use EXTRACT_ELEMENT rather than assuming the operand is a BUILD_PAIR (if it is then getNode will automagically simplify the EXTRACT_ELEMENT). This way LowerATOMIC_BINARY_64 usable from LegalizeTypes. llvm-svn: 57831
* Fix typo in a comment.Matthijs Kooijman2008-10-201-1/+1
| | | | llvm-svn: 57829
* Remove another stale comment.Matthijs Kooijman2008-10-201-3/+1
| | | | llvm-svn: 57828
* Remove an inappropriate (probably outdated) comment.Matthijs Kooijman2008-10-201-3/+1
| | | | llvm-svn: 57827
* Fix spelling error.Matthijs Kooijman2008-10-201-1/+1
| | | | llvm-svn: 57820
* Set N->OperandList to 0 after deletion. Otherwise, it's possible that it willBill Wendling2008-10-191-15/+26
| | | | | | be either deleted or referenced afterwards. llvm-svn: 57786
* Fix comment. Other formatting changes. No functionality changes.Bill Wendling2008-10-191-5/+6
| | | | llvm-svn: 57785
* Vector shuffle mask elements may be "undef". HandleDuncan Sands2008-10-191-13/+24
| | | | | | this everywhere in LegalizeTypes. llvm-svn: 57783
* Use a legal integer type for vector shuffle maskDuncan Sands2008-10-191-4/+4
| | | | | | | | | elements. Otherwise LegalizeTypes will, reasonably enough, legalize the mask, which may result in it no longer being a BUILD_VECTOR node (LegalizeDAG simply ignores the legality or not of vector masks). llvm-svn: 57782
* Reapply r57699 with a fix to not crash on asms with multiple results. UnlikeChris Lattner2008-10-182-16/+58
| | | | | | | | | | the previous patch this one actually passes make check. "Fix PR2356 on PowerPC: if we have an input and output that are tied together that have different sizes (e.g. i32 and i64) make sure to reserve registers for the bigger operand." llvm-svn: 57771
* Don't truncate GlobalAddress offsets to int in debug output.Dan Gohman2008-10-182-2/+2
| | | | llvm-svn: 57770
* By min, I mean max.Evan Cheng2008-10-181-1/+1
| | | | llvm-svn: 57766
* When creating intervals, leave min(1, numdefs) holes after each instruction.Evan Cheng2008-10-181-5/+13
| | | | llvm-svn: 57765
* Make llvm memory barrier available as an intrinsicMon P Wang2008-10-181-1/+2
| | | | llvm-svn: 57750
* Teach DAGCombine to fold constant offsets into GlobalAddress nodes,Dan Gohman2008-10-1821-85/+179
| | | | | | | | | | | | | | | | | | | | | | and add a TargetLowering hook for it to use to determine when this is legal (i.e. not in PIC mode, etc.) This allows instruction selection to emit folded constant offsets in more cases, such as the included testcase, eliminating the need for explicit arithmetic instructions. This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp that attempted to achieve the same effect, but wasn't as effective. Also, fix handling of offsets in GlobalAddressSDNodes in several places, including changing GlobalAddressSDNode's offset from int to int64_t. The Mips, Alpha, Sparc, and CellSPU targets appear to be unaware of GlobalAddress offsets currently, so set the hook to false on those targets. llvm-svn: 57748
* Revert r57699. It's causing regressions inDan Gohman2008-10-182-54/+15
| | | | | | | test/CodeGen/X86/2008-09-17-inline-asm-1.ll and a few others, and it breaks the llvm-gcc build. llvm-svn: 57747
* Use the opcode predicates, instead of duplicating the code.Dan Gohman2008-10-171-3/+3
| | | | llvm-svn: 57735
* This is now partly done.Dan Gohman2008-10-171-1/+1
| | | | llvm-svn: 57734
* This is done.Dan Gohman2008-10-171-10/+0
| | | | llvm-svn: 57733
* Factor out the code for mapping LLVM IR condition opcodes toDan Gohman2008-10-172-34/+47
| | | | | | ISD condition opcodes into helper functions. llvm-svn: 57726
* Add implicit defs of XMM8 to XMM15 on 32-bit call instructions. While this ↵Evan Cheng2008-10-171-1/+2
| | | | | | is not technically true, it tells tblgen that these instructions "clobber" the entire XMM register file. llvm-svn: 57723
* Add RCBarriers to TargetInstrDesc. It's a list of register classes the given ↵Evan Cheng2008-10-173-6/+79
| | | | | | | | instruction can "clobber". For example, on x86 the call instruction can modify all of the XMM and fp stack registers. TableGen has been taught to generate the lists from instruction definitions. llvm-svn: 57722
* Fix PR2898. Spiller delete a store for reuse before it knows for sure the ↵Evan Cheng2008-10-172-11/+155
| | | | | | | | reuse happened. Patch by Lang Hames! llvm-svn: 57720
* add support for 128 bit aggregates.Chris Lattner2008-10-171-0/+1
| | | | llvm-svn: 57715
* The Dwarf writer was comparing mangled and unmangled names for C++ code when weBill Wendling2008-10-172-1/+62
| | | | | | | | | have an unreachable block in a function. This was triggering the assert. This is a horrid hack to cover this up. Oh! for a good debug info architecture! llvm-svn: 57714
* Added MemIntrinsicNode which is useful to represent target intrinsics thatMon P Wang2008-10-173-8/+121
| | | | | | touches memory and need an associated MemOperand llvm-svn: 57712
* Factor out the code for mapping LLVM IR condition opcodes toDan Gohman2008-10-171-126/+61
| | | | | | ISD condition opcodes into helper functions. llvm-svn: 57710
* add support for 128 bit inputs on both x86-64 and x86-32.Chris Lattner2008-10-171-9/+6
| | | | llvm-svn: 57709
* Fix a bug where the x86 backend would reject 64-bit r constraints whenChris Lattner2008-10-172-1/+10
| | | | | | | in 32-bit mode instead of assigning a register pair. This has nothing to do with PR2356, but I happened to notice it while working on it. llvm-svn: 57704
* Fix PR2356 on PowerPC: if we have an input and output that are tied togetherChris Lattner2008-10-172-15/+54
| | | | | | | that have different sizes (e.g. i32 and i64) make sure to reserve registers for the bigger operand. llvm-svn: 57699
* remove an xfailed test.Chris Lattner2008-10-171-26/+0
| | | | llvm-svn: 57695
* remove this test: it is xfailed anyway, and is failing for a reasonChris Lattner2008-10-171-18/+0
| | | | | | other than why it was xfailed. llvm-svn: 57694
* Fix lfence and mfence encoding. These look like MRM5r and MRM6r instructions ↵Evan Cheng2008-10-172-5/+17
| | | | | | except they do not have any operands. The RegModRM byte is encoded with register number 0. llvm-svn: 57692
* getX86RegNum has long been moved to X86RegisterInfo.Evan Cheng2008-10-171-1/+0
| | | | llvm-svn: 57691
* refactor some code into a helper method, no functionality change.Chris Lattner2008-10-171-25/+40
| | | | llvm-svn: 57690
* Keep track of *which* input constraint matches an outputChris Lattner2008-10-175-14/+25
| | | | | | | constraint. Reject asms where an output has multiple input constraints tied to it. llvm-svn: 57687
* add an assert so that PR2356 explodes instead of running off anChris Lattner2008-10-173-6/+34
| | | | | | | array. Improve some minor comments, refactor some helpers in AsmOperandInfo. No functionality change for valid code. llvm-svn: 57686
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