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* Print uint64_t -debug text correctly on 32-bit hostsTim Northover2013-05-191-5/+5
| | | | | | | | On 32-bit hosts %p can print garbage when given a uint64_t, we should use %llx instead. This only affects the output of the debugging text produced by lli. llvm-svn: 182209
* Unsupported remote JIT on ARMRenato Golin2013-05-189-6/+17
| | | | llvm-svn: 182201
* isKnownToBeAPowerOfTwo: (X & Y) + Y is a power of 2 or zero if y is also.David Majnemer2013-05-182-0/+25
| | | | | | | This is useful if something that looks like (x & (1 << y)) ? 64 : 32 is the divisor in a modulo operation. llvm-svn: 182200
* LoopVectorize: Handle single edge PHIsArnold Schwaighofer2013-05-182-4/+26
| | | | | | | | We might encouter single edge PHIs - handle them with an identity select. Fixes PR15990. llvm-svn: 182199
* docs/Passes: fix some typosDmitri Gribenko2013-05-181-4/+4
| | | | | | Patch by Yacine Belkadi. llvm-svn: 182197
* Add basic support for ELF32-ppc relocations to llvm-dwarfdump.Benjamin Kramer2013-05-182-0/+17
| | | | | | Should help the ppc32 buildbot. llvm-svn: 182194
* Check InlineAsm clobbers in PPCCTRLoopsHal Finkel2013-05-182-0/+53
| | | | | | | | We don't need to reject all inline asm as using the counter register (most does not). Only those that explicitly clobber the counter register need to prevent the transformation. llvm-svn: 182191
* AArch64: add CMake dependency to fix very parallel buildsTim Northover2013-05-181-0/+2
| | | | llvm-svn: 182190
* X86: Bad peephole interaction between adc, MOV32r0David Majnemer2013-05-182-3/+45
| | | | | | | | | | | | | | | | The peephole tries to reorder MOV32r0 instructions such that they are before the instruction that modifies EFLAGS. The problem is that the peephole does not consider the case where the instruction that modifies EFLAGS also depends on the previous state of EFLAGS. Instead, walk backwards until we find an instruction that has a def for EFLAGS but does not have a use. If we find such an instruction, insert the MOV32r0 before it. If it cannot find such an instruction, skip the optimization. llvm-svn: 182184
* Remove duplicated commentMatt Arsenault2013-05-181-5/+0
| | | | | | The same comment is already made in the header llvm-svn: 182181
* Add LLVMContext argument to getSetCCResultTypeMatt Arsenault2013-05-1830-100/+122
| | | | llvm-svn: 182180
* Support unaligned load/store on more ARM targetsJF Bastien2013-05-174-140/+193
| | | | | | | | | | | | | | | | | | | | | This patch matches GCC behavior: the code used to only allow unaligned load/store on ARM for v6+ Darwin, it will now allow unaligned load/store for v6+ Darwin as well as for v7+ on Linux and NaCl. The distinction is made because v6 doesn't guarantee support (but LLVM assumes that Apple controls hardware+kernel and therefore have conformant v6 CPUs), whereas v7 does provide this guarantee (and Linux/NaCl behave sanely). The patch keeps the -arm-strict-align command line option, and adds -arm-no-strict-align. They behave similarly to GCC's -mstrict-align and -mnostrict-align. I originally encountered this discrepancy in FastIsel tests which expect unaligned load/store generation. Overall this should slightly improve performance in most cases because of reduced I$ pressure. llvm-svn: 182175
* Fix the configure build.Rafael Espindola2013-05-171-1/+1
| | | | llvm-svn: 182172
* Convert obj2yaml to use yamlio.Rafael Espindola2013-05-177-761/+580
| | | | llvm-svn: 182169
* Fix the build in c++11 mode.Rafael Espindola2013-05-171-2/+2
| | | | | | | | | | | | The errors were: non-constant-expression cannot be narrowed from type 'int64_t' (aka 'long') to 'uint32_t' (aka 'unsigned int') in initializer list and non-constant-expression cannot be narrowed from type 'long' to 'uint32_t' (aka 'unsigned int') in initializer list llvm-svn: 182168
* Replace redundant codeMatt Arsenault2013-05-171-7/+2
| | | | | | | Use EVT::changeExtendedVectorElementTypeToInteger instead of doing the same thing that it does llvm-svn: 182165
* Add missing -*- C++ -*- to headersMatt Arsenault2013-05-173-5/+5
| | | | llvm-svn: 182164
* Add missing verb to comment in PassNameParser.hDerek Schuff2013-05-171-3/+3
| | | | | | Patch by Mark Seaborn. llvm-svn: 182131
* R600: Lower int_load_input to copyFromReg instead of Register nodeVincent Lejeune2013-05-172-1/+126
| | | | | | | It solves a bug uncovered by dot4 patch where the register class of int_load_input use was ignored. llvm-svn: 182130
* R600: Use bottom up scheduling algorithmVincent Lejeune2013-05-1719-42/+56
| | | | llvm-svn: 182129
* R600: Use depth first scheduling algorithmVincent Lejeune2013-05-174-81/+33
| | | | | | | It should increase PV substitution opportunities and lower gpr usage (pending computations path are "flushed" sooner) llvm-svn: 182128
* R600: Replace big texture opcode switch in scheduler by usesTC/usesVCVincent Lejeune2013-05-171-23/+3
| | | | llvm-svn: 182127
* R600: Relax some vector constraints on Dot4.Vincent Lejeune2013-05-1711-27/+281
| | | | | | | | | | Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register coalescer to remove some unneeded COPY. This patch also defines some structures/functions that can be used to handle every vector instructions (CUBE, Cayman special instructions...) in a similar fashion. llvm-svn: 182126
* R600: Improve texture handlingVincent Lejeune2013-05-1712-217/+741
| | | | llvm-svn: 182125
* R600: Rename 128 bit registers.Vincent Lejeune2013-05-173-26/+25
| | | | | | | | | Almost all instructions that takes a 128 bits reg as input (fetch, export...) have the abilities to swizzle their argument and output. Instead of printing default swizzle for each 128 bits reg, rename T*.XYZW to T* and let instructions print potentially optimized swizzles themselves. llvm-svn: 182124
* R600: Some factorizationVincent Lejeune2013-05-175-203/+221
| | | | llvm-svn: 182123
* R600: Factorize Fetch size limit inside AMDGPUSubTargetVincent Lejeune2013-05-174-13/+13
| | | | llvm-svn: 182122
* R600: prettier dump of clampVincent Lejeune2013-05-172-4/+4
| | | | llvm-svn: 182121
* R600: Fix encoding for R600 family GPUsTom Stellard2013-05-172-0/+31
| | | | | | | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> https://bugs.freedesktop.org/show_bug.cgi?id=64193 https://bugs.freedesktop.org/show_bug.cgi?id=64257 https://bugs.freedesktop.org/show_bug.cgi?id=64320 NOTE: This is a candidate for the 3.3 branch. llvm-svn: 182113
* R600: Pass MCSubtargetInfo reference to R600CodeEmitterTom Stellard2013-05-173-6/+10
| | | | llvm-svn: 182112
* [Sparc] Implements hasReservedCallFrame and hasFP.Venkatraman Govindaraju2013-05-173-1/+33
| | | | | | | This is to generate correct framesetup code when the function has variable sized allocas. llvm-svn: 182108
* X86: Make shuffle -> shift conversion more aggressive about undefs.Benjamin Kramer2013-05-173-20/+54
| | | | | | | | | | | Shuffles that only move an element into position 0 of the vector are common in the output of the loop vectorizer and often generate suboptimal code when SSSE3 is not available. Lower them to vector shifts if possible. We still prefer palignr over psrldq because it has higher throughput on sandybridge. llvm-svn: 182102
* FileCheckize test.Benjamin Kramer2013-05-171-5/+15
| | | | llvm-svn: 182101
* LoopVectorize: Simplify code. No functionality change.Benjamin Kramer2013-05-171-21/+5
| | | | llvm-svn: 182100
* r182085 introduced a change that triggered an assertion on ARM. This is an ↵David Tweed2013-05-171-2/+4
| | | | | | | | immediate fix which doesn't resolve the deeper problem. llvm-svn: 182098
* [PowerPC] Fix hi/lo encoding in old-style code emitterUlrich Weigand2013-05-174-33/+17
| | | | | | | | | | | | | | | | | This patch implements the equivalent change to r182091/r182092 in the old-style code emitter. Instead of having two separate 16-bit immediate encoding routines depending on the instruction, this patch introduces a single encoder that checks the machine operand flags to decide whether the low or high half of a symbol address is required. Since now both encoders make no further distinction between "symbolLo" and "symbolHi", the .td operand can now use a single getS16ImmEncoding method. Tested by running the old-style JIT tests on 32-bit Linux. llvm-svn: 182097
* [PowerPC] Merge/rename PPC fixup typesUlrich Weigand2013-05-175-53/+42
| | | | | | | | | | | | | | Now that fixup_ppc_ha16 and fixup_ppc_lo16 are being treated exactly the same everywhere, it no longer makes sense to have two fixup types. This patch merges them both into a single type fixup_ppc_half16, and renames fixup_ppc_lo16_ds to fixup_ppc_half16ds for consistency. (The half16 and half16ds names are taken from the description of relocation types in the PowerPC ABI.) No change in code generation expected. llvm-svn: 182092
* [PowerPC] Fix processing of ha16/lo16 fixupsUlrich Weigand2013-05-174-7/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current PowerPC MC back end distinguishes between fixup_ppc_ha16 and fixup_ppc_lo16, which are determined by the instruction the fixup applies to, and uses this distinction to decide whether a fixup ought to resolve to the high or the low part of a symbol address. This isn't quite correct, however. It is valid -if unusual- assembler to use, e.g. li 1, symbol@ha or lis 1, symbol@l Whether the high or the low part of the address is used depends solely on the @ suffix, not on the instruction. In addition, both li 1, symbol and lis 1, symbol are valid, assuming the symbol address fits into 16 bits; again, both will then refer to the actual symbol value (so li will load the value itself, while lis will load the value shifted by 16). To fix this, two places need to be adapted. If the fixup cannot be resolved at assembler time, a relocation needs to be emitted via PPCELFObjectWriter::getRelocType. This routine already looks at the VK_ type to determine the relocation. The only problem is that will reject any _LO modifier in a ha16 fixup and vice versa. This is simply incorrect; any of those modifiers ought to be accepted for either fixup type. If the fixup *can* be resolved at assembler time, adjustFixupValue currently selects the high bits of the symbol value if the fixup type is ha16. Again, this is incorrect; see the above example lis 1, symbol Now, in theory we'd have to respect a VK_ modifier here. However, in fact common code never even attempts to resolve symbol references using any nontrivial VK_ modifier at assembler time; it will always fall back to emitting a reloc and letting the linker handle it. If this ever changes, presumably there'd have to be a target callback to resolve VK_ modifiers. We'd then have to handle @ha etc. there. llvm-svn: 182091
* Fix a typo (ouput => output)Sylvestre Ledru2013-05-171-1/+1
| | | | llvm-svn: 182090
* Don't cast away constness.Benjamin Kramer2013-05-171-2/+2
| | | | llvm-svn: 182086
* Minor changes to the MCJITTest unittests to use the correct API for finalizingDavid Tweed2013-05-1713-33/+48
| | | | | | | the JIT object (including XFAIL an ARM test that now needs fixing). Also renames internal function for consistency. llvm-svn: 182085
* R600/SI: return undef instead of null for skipped argumentsChristian Konig2013-05-171-2/+2
| | | | | | | | | | | This is a candidate for the stable branch. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=64694 Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182084
* [Sparc] Prevent instructions that defines or uses %o7 to be in call's delay ↵Venkatraman Govindaraju2013-05-162-5/+26
| | | | | | slot. llvm-svn: 182063
* Generate debug info for by-value struct args even if they are not used.Adrian Prantl2013-05-162-1/+133
| | | | | | radar://problem/13865940 llvm-svn: 182062
* llvm-objdump: Initialize MCDisassembler once instead of for each section.Ahmed Bougacha2013-05-161-45/+45
| | | | llvm-svn: 182054
* [mips] Improve instruction selection for pattern (store (fp_to_sint $src), ↵Akira Hatanaka2013-05-164-9/+92
| | | | | | | | | | | | | | | | | $ptr). Previously, three instructions were needed: trunc.w.s $f0, $f2 mfc1 $4, $f0 sw $4, 0($2) Now we need only two: trunc.w.s $f0, $f2 swc1 $f0, 0($2) llvm-svn: 182053
* Remove addFrameMove.Rafael Espindola2013-05-168-130/+88
| | | | | | | Now that we have good testing, remove addFrameMove and create cfi instructions directly. llvm-svn: 182052
* More test coverage for addFrameMove.Rafael Espindola2013-05-161-0/+15
| | | | llvm-svn: 182051
* [mips] Factor out unaligned store lowering code.Akira Hatanaka2013-05-161-10/+14
| | | | llvm-svn: 182050
* Fix cpu on test CodeGen/PowerPC/ctrloop-fp64.llHal Finkel2013-05-161-1/+1
| | | | | | We need ppc instead of generic to override native features on ppc machines. llvm-svn: 182049
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