| Commit message (Collapse) | Author | Age | Files | Lines |
| ... | |
| |
|
|
|
|
|
|
| |
unsigned overflow (e.g. due to a negative array index), but
the scales on array size multiplications are known to not
sign wrap.
llvm-svn: 125409
|
| |
|
|
| |
llvm-svn: 125408
|
| |
|
|
|
|
| |
on the host OS. Reviewed by dgregor.
llvm-svn: 125406
|
| |
|
|
|
|
| |
This avoids moving each element to the integer register file and calling __divsi3 etc. on it.
llvm-svn: 125402
|
| |
|
|
|
|
| |
that the condition is not a vector.
llvm-svn: 125398
|
| |
|
|
|
|
|
| |
Add more folding patterns to constant expressions of vector selects and vector
bitcasts.
llvm-svn: 125393
|
| |
|
|
|
|
|
|
|
|
|
| |
The bug happens when the DAGCombiner attempts to optimize one of the patterns
of the SUB opcode. It tries to create a zero of type v2i64. This type is legal
on 32bit machines, but the initializer of this vector (i64) is target dependent.
Currently, the initializer attempts to create an i64 zero constant, which fails.
Added a flag to tell the DAGCombiner to create a legal zero, if we require that
the pass would generate legal types.
llvm-svn: 125391
|
| |
|
|
| |
llvm-svn: 125389
|
| |
|
|
| |
llvm-svn: 125388
|
| |
|
|
| |
llvm-svn: 125385
|
| |
|
|
|
|
|
| |
objects, since they'll end up using the implicit conversion to "bool"
and causing some very "fun" surprises.
llvm-svn: 125380
|
| |
|
|
|
|
|
| |
a loop when unswitching it. It only does this in the complex case, because
everything should be fine already in the simple case.
llvm-svn: 125369
|
| |
|
|
| |
llvm-svn: 125368
|
| |
|
|
| |
llvm-svn: 125367
|
| |
|
|
|
|
| |
flag. Noticed by Jin Gu Kang!
llvm-svn: 125366
|
| |
|
|
|
|
| |
as other constantexpr flags, reducing redundancy.
llvm-svn: 125365
|
| |
|
|
| |
llvm-svn: 125363
|
| |
|
|
| |
llvm-svn: 125361
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This
define float @foo(float %x, float %y) nounwind readnone {
entry:
%0 = tail call float @copysignf(float %x, float %y) nounwind readnone
ret float %0
}
Was compiled to:
vmov s0, r1
bic r0, r0, #-2147483648
vmov s1, r0
vcmpe.f32 s0, #0
vmrs apsr_nzcv, fpscr
it lt
vneglt.f32 s1, s1
vmov r0, s1
bx lr
This fails to copy the sign of -0.0f because it's lost during the float to int
conversion. Also, it's sub-optimal when the inputs are in GPR registers.
Now it uses integer and + or operations when it's profitable. And it's correct!
lsrs r1, r1, #31
bfi r0, r1, #31, #1
bx lr
rdar://8984306
llvm-svn: 125357
|
| |
|
|
| |
llvm-svn: 125327
|
| |
|
|
| |
llvm-svn: 125325
|
| |
|
|
|
|
| |
passes. Fixes PR9112. Patch by Jakub Staszak!
llvm-svn: 125319
|
| |
|
|
|
|
| |
iv-users twice.
llvm-svn: 125318
|
| |
|
|
| |
llvm-svn: 125317
|
| |
|
|
| |
llvm-svn: 125316
|
| |
|
|
|
|
|
| |
largely completes support for 128-bit fallback lowering for code that
is not 256-bit ready.
llvm-svn: 125315
|
| |
|
|
|
|
| |
proper fix soon
llvm-svn: 125305
|
| |
|
|
| |
llvm-svn: 125304
|
| |
|
|
|
|
| |
with some small modifications by me.
llvm-svn: 125292
|
| |
|
|
| |
llvm-svn: 125284
|
| |
|
|
| |
llvm-svn: 125279
|
| |
|
|
|
|
| |
Unixen and Cygwin do not need it.
llvm-svn: 125277
|
| |
|
|
| |
llvm-svn: 125274
|
| |
|
|
| |
llvm-svn: 125273
|
| |
|
|
| |
llvm-svn: 125272
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
gep to explicit addressing, we know that none of the intermediate
computation overflows.
This could use review: it seems that the shifts certainly wouldn't
overflow, but could the intermediate adds overflow if there is a
negative index?
Previously the testcase would instcombine to:
define i1 @test(i64 %i) {
%p1.idx.mask = and i64 %i, 4611686018427387903
%cmp = icmp eq i64 %p1.idx.mask, 1000
ret i1 %cmp
}
now we get:
define i1 @test(i64 %i) {
%cmp = icmp eq i64 %i, 1000
ret i1 %cmp
}
llvm-svn: 125271
|
| |
|
|
|
|
|
| |
for NSW/NUW binops to follow the pattern of exact binops. This
allows someone to use Builder.CreateAdd(x, y, "tmp", MaybeNUW);
llvm-svn: 125270
|
| |
|
|
|
|
|
|
|
|
|
| |
exact/nsw/nuw shifts and have instcombine infer them when it can prove
that the relevant properties are true for a given shift without them.
Also, a variety of refactoring to use the new patternmatch logic thrown
in for good luck. I believe that this takes care of a bunch of related
code quality issues attached to PR8862.
llvm-svn: 125267
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
optimizations to be much more aggressive in the face of
exact/nsw/nuw div and shifts. For example, these (which
are the same except the first is 'exact' sdiv:
define i1 @sdiv_icmp4_exact(i64 %X) nounwind {
%A = sdiv exact i64 %X, -5 ; X/-5 == 0 --> x == 0
%B = icmp eq i64 %A, 0
ret i1 %B
}
define i1 @sdiv_icmp4(i64 %X) nounwind {
%A = sdiv i64 %X, -5 ; X/-5 == 0 --> x == 0
%B = icmp eq i64 %A, 0
ret i1 %B
}
compile down to:
define i1 @sdiv_icmp4_exact(i64 %X) nounwind {
%1 = icmp eq i64 %X, 0
ret i1 %1
}
define i1 @sdiv_icmp4(i64 %X) nounwind {
%X.off = add i64 %X, 4
%1 = icmp ult i64 %X.off, 9
ret i1 %1
}
This happens when you do something like:
(ptr1-ptr2) == 42
where the pointers are pointers to non-unit types.
llvm-svn: 125266
|
| |
|
|
|
|
| |
conversions". :)
llvm-svn: 125265
|
| |
|
|
|
|
|
|
|
|
| |
and generally tidying things up. Only very trivial functionality changes
like now doing (-1 - A) -> (~A) for vectors too.
InstCombineAddSub.cpp | 296 +++++++++++++++++++++-----------------------------
1 file changed, 126 insertions(+), 170 deletions(-)
llvm-svn: 125264
|
| |
|
|
|
|
|
| |
are shifting out since they do require them to be zeros. Similarly
for NUW/NSW bits of shl
llvm-svn: 125263
|
| |
|
|
|
|
| |
add a missing check when considering whether it's profitable to commute. rdar://8977508.
llvm-svn: 125259
|
| |
|
|
| |
llvm-svn: 125257
|
| |
|
|
| |
llvm-svn: 125256
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Natural Loop Information
Loop Pass Manager
Canonicalize natural loops
Scalar Evolution Analysis
Loop Pass Manager
Induction Variable Users
Canonicalize natural loops
Induction Variable Users
Loop Strength Reduction
into this:
Scalar Evolution Analysis
Loop Pass Manager
Canonicalize natural loops
Induction Variable Users
Loop Strength Reduction
This fixes <rdar://problem/8869639>. I also filed PR9184 on doing this sort of
thing automatically, but it seems easier to just change the ordering of the
passes if this is the only case.
llvm-svn: 125254
|
| |
|
|
|
|
|
|
|
|
| |
When matching operands for a candidate opcode match in the auto-generated
AsmMatcher, check each operand against the expected operand match class.
Previously, operands were classified independently of the opcode being
handled, which led to difficulties when operand match classes were
more complicated than simple subclass relationships.
llvm-svn: 125245
|
| |
|
|
|
|
|
| |
Loop splitting is better handled by the more generic global region splitting
based on the edge bundle graph.
llvm-svn: 125243
|
| |
|
|
|
|
| |
I have another way to achieve the same goal.
llvm-svn: 125239
|
| |
|
|
| |
llvm-svn: 125238
|