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* [AArch64] Improve code generation for logical instructions takingAkira Hatanaka2017-04-208-58/+280
| | | | | | | | | | | | | | | | immediate operands. This commit adds an AArch64 dag-combine that optimizes code generation for logical instructions taking immediate operands. The optimization uses demanded bits to change a logical instruction's immediate operand so that the immediate can be folded into the immediate field of the instruction. rdar://problem/18231627 Differential Revision: https://reviews.llvm.org/D5591 llvm-svn: 300913
* [InstCombine] function names start with lower-case letter; NFCSanjay Patel2017-04-202-3/+3
| | | | | | Forgot to make this fix with the signature change in r300911. llvm-svn: 300912
* [InstCombine] allow shl+shr demanded bits folds with splat constantsSanjay Patel2017-04-203-28/+21
| | | | llvm-svn: 300911
* [InstCombine] add tests for shl+shr demanded bits splat vector folds; NFCSanjay Patel2017-04-201-2/+24
| | | | llvm-svn: 300907
* AArch64: lower "fence singlethread" to a pure compiler barrier.Tim Northover2017-04-204-0/+14
| | | | | | | | Single-threaded fences aren't required to provide any synchronization with other processing elements so there's no need for a DMB. They should still be a barrier for compiler optimizations though. llvm-svn: 300905
* ARM: lower "fence singlethread" to a pure compiler barrier.Tim Northover2017-04-203-1/+28
| | | | | | | | Single-threaded fences aren't required to provide any synchronization with other processing elements so there's no need for a DMB. They should still be a barrier for compiler optimizations though. llvm-svn: 300904
* Use basicblock split block utility functionXinliang David Li2017-04-201-8/+2
| | | | | | | | | Instead of calling BasicBlock::SplitBasicBlock directly in CodeExtractor. Differential Revision: https://reviews.llvm.org/D32308 llvm-svn: 300899
* [InstCombine] allow shl demanded bits folds with splat constantsSanjay Patel2017-04-204-14/+9
| | | | | | More fixes are needed to enable the helper SimplifyShrShlDemandedBits(). llvm-svn: 300898
* [InstCombine] Use APInt::intersects and APInt::isSubsetOf to improve a few ↵Craig Topper2017-04-201-4/+4
| | | | | | more places in SimplifyDemandedBits. llvm-svn: 300896
* [AArch64] Whitespace/ordering fixes for Falkor machine description. NFC.Chad Rosier2017-04-201-2/+4
| | | | llvm-svn: 300893
* [AArch64] Refine Falkor machine description for pre/post-inc and stores.Chad Rosier2017-04-201-5/+5
| | | | llvm-svn: 300892
* [InstCombine] allow ashr/lshr demanded bits folds with splat constantsSanjay Patel2017-04-203-18/+19
| | | | llvm-svn: 300888
* [InstCombine] Use APInt::isSubsetOf to simplify some code in ↵Craig Topper2017-04-201-37/+27
| | | | | | | | SimplifyDemandedBits. NFC This allows us to use less temporary APInt for And and Invert operations. llvm-svn: 300885
* [InstCombine] add tests for demanded bits ashr/lshr splat constants; NFCSanjay Patel2017-04-201-0/+22
| | | | llvm-svn: 300884
* Don't emit locations that need a DW_OP_stack_value in DWARF 2 & 3.Adrian Prantl2017-04-203-1/+19
| | | | | | https://bugs.llvm.org/show_bug.cgi?id=32382 llvm-svn: 300883
* [Support] Make asan poisoning for recyclers more aggressive by also ↵Benjamin Kramer2017-04-202-6/+4
| | | | | | poisoning the 'next' pointer. llvm-svn: 300882
* Remove stray ^S. NFC.Benjamin Kramer2017-04-201-1/+1
| | | | llvm-svn: 300880
* [DWARF] Fix a couple of typosPaul Robinson2017-04-201-2/+2
| | | | llvm-svn: 300879
* ARM: handle post-indexed NEON ops where the offset isn't the access width.Tim Northover2017-04-2010-82/+148
| | | | | | | | | | | Before, we assumed that any ConstantInt offset was precisely the access width, so we could use the "[rN]!" form. ISelLowering only ever created that kind, but further simplification during combining could lead to unexpected constants and incorrect codegen. Should fix PR32658. llvm-svn: 300878
* VarStreamArrayIterator needed non-const operator* overload.Adrian McCarthy2017-04-201-0/+5
| | | | | | | | | Without this change, the operator-> provided by iterator_facade lost type qualifiers. Differential Revision: https://reviews.llvm.org/D32235 llvm-svn: 300877
* [InstCombine] Remove redundant code from SimplifyDemandedBits handling for ↵Craig Topper2017-04-201-18/+0
| | | | | | Or. The code above it is equivalent if you work through the bitwise math. llvm-svn: 300876
* [DWARF] Versioning for DWARF constants; verify FORMsPaul Robinson2017-04-209-748/+800
| | | | | | | | | | | | | Associate the version-when-defined with definitions of standard DWARF constants. Identify the "vendor" for DWARF extensions. Use this information to verify FORMs in .debug_abbrev are defined as of the DWARF version specified in the associated unit. Removed two tests that had specified DWARF v1 (which essentially does not exist). Differential Revision: http://reviews.llvm.org/D30785 llvm-svn: 300875
* [go bindings] Rmove duplicated conversion function definitions after r300843.Benjamin Kramer2017-04-201-2/+0
| | | | llvm-svn: 300872
* [AArch64] Improve scheduling of logical operations on Falkor.Chad Rosier2017-04-201-0/+6
| | | | llvm-svn: 300871
* [Thumb-1] Fix corner cases for compressed jump tablesWeiming Zhao2017-04-201-0/+9
| | | | | | | | | | | | | | | | | | | | | Summary: When synthesized TBB/TBH is expanded, we need to avoid the case of: BaseReg is redefined after the load of branching target. E.g.: %R2 = tLEApcrelJT <jt#1> %R1 = tLDRr %R1, %R2 ==> %R2 = tLEApcrelJT <jt#1> %R2 = tLDRspi %SP, 12 %R2 = tLDRspi %SP, 12 tBR_JTr %R1 tTBB_JT %R2, %R1 ` Reviewers: jmolloy Reviewed By: jmolloy Subscribers: llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D32250 llvm-svn: 300870
* [CodeExtractor] Remove a bunch of unneeded constructors.Davide Italiano2017-04-202-40/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D32305 llvm-svn: 300869
* [Recycler] Add asan/msan annotations.Benjamin Kramer2017-04-203-2/+13
| | | | | | | | | | This enables use after free and uninit memory checking for memory returned by a recycler. SelectionDAG currently relies on the opcode of a free'd node being ISD::DELETED_NODE, so poke a hole in the asan poison for SDNode opcodes. This means that we won't find some issues, but only in SDag. llvm-svn: 300868
* Fix use-after-frees on memory allocated in a Recycler.Benjamin Kramer2017-04-205-12/+16
| | | | | | | | This will become asan errors once the patch lands that poisons the memory after free. The x86 change is a hack, but I don't see how to solve this properly at the moment. llvm-svn: 300867
* Fixing outdated comment [NFC]Artyom Skrobov2017-04-201-5/+1
| | | | | | | Since r32105 back in 2006, RegisterPass doesn't support passes without a default constructor. llvm-svn: 300866
* Fix formatting of constrained FP intrinsic documentationAndrew Kaylor2017-04-201-0/+2
| | | | llvm-svn: 300865
* CodeGen: Let frame index value type match alloca addr spaceYaxun Liu2017-04-204-7/+68
| | | | | | | | | | | | | | | | | | | | | | Recently alloca address space has been added to data layout. Due to this change, pointer returned by alloca may have different size as pointer in address space 0. However, currently the value type of frame index is assumed to be of the same size as pointer in address space 0. This patch fixes that. Most targets assume alloca returning pointer in address space 0, which is the default alloca address space. Therefore it is NFC for them. AMDGCN target with amdgiz environment requires this change since it assumes alloca returning pointer to addr space 5 and its size is 32, which is different from the size of pointer in addr space 0 which is 64. Differential Revision: https://reviews.llvm.org/D32021 llvm-svn: 300864
* Remove duplicate AttributeList::removeAttributes implementationReid Kleckner2017-04-201-63/+12
| | | | | | | | | | | | | | | Have the AttributeList overload delegate to the AttrBuilder one. Simplify the AttrBuilder overload by avoiding getSlotAttributes, which creates temporary AttributeLists. Simplify `AttrBuilder::removeAttributes(AttributeList, unsigned)` by using getAttributes instead of manually iterating over slots. Extracted from https://reviews.llvm.org/D32262 NFC llvm-svn: 300863
* [DAGCombiner] use more local variables in isAlias(); NFCISanjay Patel2017-04-201-9/+11
| | | | llvm-svn: 300860
* [WebAssembly] Add known failures for wasm object file backendSam Clegg2017-04-201-0/+28
| | | | | | | | Subscribers: jfb, dschuff Differential Revision: https://reviews.llvm.org/D32300 llvm-svn: 300859
* Resubmit "[BitVector] Add operator<<= and operator>>=."Zachary Turner2017-04-203-0/+287
| | | | | | | | | This was failing due to the use of assigning a Mask to an unsigned, rather than to a BitWord. But most systems do not have sizeof(unsigned) == sizeof(unsigned long), so the mask was getting truncated. llvm-svn: 300857
* [APInt] Rename getSignBit to getSignMaskCraig Topper2017-04-2018-102/+102
| | | | | | | | getSignBit is a static function that creates an APInt with only the sign bit set. getSignMask seems like a better name to convey its functionality. In fact several places use it and then store in an APInt named SignMask. Differential Revision: https://reviews.llvm.org/D32108 llvm-svn: 300856
* [SVE] Fix mismatched sign comparison warning in unit test from r300842.Amara Emerson2017-04-201-2/+2
| | | | llvm-svn: 300855
* [DAGCombiner] fix variable names in isAlias(); NFCISanjay Patel2017-04-201-27/+28
| | | | | | | We started with zero-based params and switched to one-based locals... Also, variables start with a capital and functions do not. llvm-svn: 300854
* Revert "[BitVector] Add operator<<= and operator>>=."Zachary Turner2017-04-203-287/+0
| | | | | | | This is causing test failures on Linux / BSD systems. Reverting while I investigate. llvm-svn: 300852
* [APInt] Add isSubsetOf method that can check if one APInt is a subset of ↵Craig Topper2017-04-204-1/+49
| | | | | | | | | | | | | | another without creating temporary APInts This question comes up in many places in SimplifyDemandedBits. This makes it easy to ask without allocating additional temporary APInts. The BitVector class provides a similar functionality through its (IMHO badly named) test(const BitVector&) method. Though its output polarity is reversed. I've provided one example use case in this patch. I plan to do more as a follow up. Differential Revision: https://reviews.llvm.org/D32258 llvm-svn: 300851
* [DAGCombiner] give names to repeated calcs in isAlias(); NFCISanjay Patel2017-04-201-13/+11
| | | | llvm-svn: 300850
* In SimplifyDemandedUseBits, use computeKnownBits directly to handle ConstantsCraig Topper2017-04-201-15/+4
| | | | | | | | | | | | Currently we don't explicitly process ConstantDataSequential, ConstantAggregateZero, or ConstantVector, or Undef before applying the Depth limit. Instead they occur after the depth check in the non-instruction path. For the constant types that we do handle, the code is replicated from computeKnownBits. This patch fixes the missing constant handling and the reduces the amount of code by just using computeKnownBits directly for any type of Constant. Differential Revision: https://reviews.llvm.org/D32123 llvm-svn: 300849
* [BitVector] Add operator<<= and operator>>=.Zachary Turner2017-04-203-0/+287
| | | | | | Differential Revision: https://reviews.llvm.org/D32244 llvm-svn: 300848
* [globalisel] Enable tracing the legalizer with --debug-only=legalize-mirDaniel Sanders2017-04-202-6/+32
| | | | | | | | | | | | Reviewers: t.p.northover, ab, qcolombet, aditya_nandakumar, rovka, kristof.beyls Reviewed By: kristof.beyls Subscribers: dberris, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D31750 llvm-svn: 300847
* Introduce LLVMDIBuilderRefAmaury Sechet2017-04-202-0/+10
| | | | | | | | | | | | | | | | | Summary: This patch adds a definition of `LLVMDIBuilderRef` that represents an `llvm::DIBuilder`. Authored by Harlan Haskins Reviewers: deadalnix, aprantl, probinson, dblaikie, echristo, whitequark Reviewed By: deadalnix, whitequark Subscribers: CodaFi, loladiro Differential Revision: https://reviews.llvm.org/D32122 llvm-svn: 300843
* [MVT][SVE] Scalable vector MVTs (3/3)Amara Emerson2017-04-205-12/+274
| | | | | | | | | | | | Adds MVT::ElementCount to represent the length of a vector which may be scalable, then adds helper functions that work with it. Patch by Graham Hunter. Differential Revision: https://reviews.llvm.org/D32019 llvm-svn: 300842
* [MVT][SVE] Scalable vector MVTs (2/3)Amara Emerson2017-04-206-209/+472
| | | | | | | | | | | Adds scalable vector machine value types, and updates the switch statements required for tablegen. Patch by Graham Hunter. Differential Revision: https://reviews.llvm.org/D32018 llvm-svn: 300840
* [mips][msa] Mask vectors holding shift amountsPetar Jovanovic2017-04-204-6/+724
| | | | | | | | | | | | | | | | | | | | | | | | | | | Masked vectors which hold shift amounts when creating the following nodes: ISD::SHL, ISD::SRL or ISD::SRA. Instructions that use said nodes, which have had their arguments altered are sll, srl, sra, bneg, bclr and bset. For said instructions, the shift amount or the bit position that is specified in the corresponding vector elements will be interpreted as the shift amount/bit position modulo the size of the element in bits. The problem lies in compiling with -O2 enabled, where the instructions for formats .w and .d are not generated, but are instead optimized away. In this case, having shift amounts that are either negative or greater than the element bit size results in generation of incorrect results when constant folding. We remedy this by masking the operands for the nodes mentioned above before actually creating them, so that the final result is correct before placed into the constant pool. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D31331 llvm-svn: 300839
* [MVT][SVE] Scalable vector MVTs (1/3)Amara Emerson2017-04-203-15/+20
| | | | | | | | | | | | | | | | This patch adds a few helper functions to obtain new vector value types based on existing ones without needing to care about whether they are scalable or not. I've confined their use to a few common locations right now, and targets that don't have scalable vectors should never need to care about these. Patch by Graham Hunter. Differential Revision: https://reviews.llvm.org/D32017 llvm-svn: 300838
* [ARM] Fix handling of mapping symbols when changing sectionsJohn Brawn2017-04-202-2/+19
| | | | | | | | | | | ChangeSection incorrectly registers LastEMSInfo as belonging to the previous section, not the current section. This happens to work when changing sections using .section, as the previous section is set to the current section before the call to ChangeSection, but not when using .popsection. Differential Revision: https://reviews.llvm.org/D32225 llvm-svn: 300831
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