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* AMDGPU: Move combines into separate functionsMatt Arsenault2016-12-222-152/+174
| | | | llvm-svn: 290309
* AMDGPU: Enable some f32 fadd/fsub combines for f16Matt Arsenault2016-12-224-10/+504
| | | | llvm-svn: 290308
* AMDGPU: Implement isFMAFasterThanFMulAndFAdd for f16Matt Arsenault2016-12-222-12/+43
| | | | llvm-svn: 290307
* AMDGPU: setcc test cleanupMatt Arsenault2016-12-222-234/+244
| | | | llvm-svn: 290306
* AMDGPU: Allow rcp and rsq usage with f16Matt Arsenault2016-12-223-14/+188
| | | | llvm-svn: 290302
* AMDGPU: Custom lower f16 fdivMatt Arsenault2016-12-223-17/+50
| | | | llvm-svn: 290301
* AMDGPU: Implement f16 fcanonicalizeMatt Arsenault2016-12-224-0/+181
| | | | llvm-svn: 290300
* AMDGPU: Update isFPImmLegal for f16Matt Arsenault2016-12-221-1/+2
| | | | | | I don't think this matters because ConstantFP is legal. llvm-svn: 290299
* Clear the PendingTypeTests vector after moving from it.Peter Collingbourne2016-12-221-0/+2
| | | | | | | This is to put the vector into a well defined state. Apparently the state of a vector after being moved from is valid but unspecified. Found with clang-tidy. llvm-svn: 290298
* [AArch64] Correct the check of signed 9-bit imm in getIndexedAddressParts().Haicheng Wu2016-12-222-2/+188
| | | | | | | | -256 is a legal indexed address part. Differential Revision: https://reviews.llvm.org/D27537 llvm-svn: 290296
* Pass GetAssumptionCache to InlineFunctionInfo constructorEaswaran Raman2016-12-221-1/+1
| | | | | | Differential revision: https://reviews.llvm.org/D28038 llvm-svn: 290295
* [NVVMIntrRange] Only set range metadata if none is already presentDavid Majnemer2016-12-222-0/+14
| | | | | | | The range metadata inserted by NVVMIntrRange is pessimistic, range metadata already present could be more precise. llvm-svn: 290294
* Renumber testcase metadata nodes after r290153.Adrian Prantl2016-12-22144-11342/+11678
| | | | | | | | | | | | | This patch renumbers the metadata nodes in debug info testcases after https://reviews.llvm.org/D26769. This is a separate patch because it causes so much churn. This was implemented with a python script that pipes the testcases through llvm-as - | llvm-dis - and then goes through the original and new output side-by side to insert all comments at a close-enough location. Differential Revision: https://reviews.llvm.org/D27765 llvm-svn: 290292
* [LLParser] Make the line field of DIMacro(File) optional.Adrian Prantl2016-12-222-2/+23
| | | | | | Otherwise these records do not survive roundtrips. llvm-svn: 290291
* Legalize metadata in legacy testcasesAdrian Prantl2016-12-211-1/+1
| | | | llvm-svn: 290288
* Legalize metadata in legacy testcasesAdrian Prantl2016-12-211-8/+7
| | | | llvm-svn: 290287
* Legalize metadata in legacy testcasesAdrian Prantl2016-12-211-1/+5
| | | | llvm-svn: 290286
* Legalize metadata in legacy testcasesAdrian Prantl2016-12-212-3/+8
| | | | llvm-svn: 290285
* [GlobalISel] Add basic Selector-emitter tblgen backend.Ahmed Bougacha2016-12-2110-7/+446
| | | | | | | | | | | | | | | | | This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
* [AsmWriter] Remove redundant cast<>s. NFC.Ahmed Bougacha2016-12-211-2/+2
| | | | llvm-svn: 290283
* [WebAssembly] Fix the opcode value for i64.rotr.Dan Gohman2016-12-211-1/+1
| | | | llvm-svn: 290281
* IR: Function summary representation for type tests.Peter Collingbourne2016-12-218-10/+102
| | | | | | | | | | | Each function summary has an attached list of type identifier GUIDs. The idea is that during the regular LTO phase we would match these GUIDs to type identifiers defined by the regular LTO module and store the resolutions in a top-level "type identifier summary" (which will be implemented separately). Differential Revision: https://reviews.llvm.org/D27967 llvm-svn: 290280
* [sancov] skip duplicated pointsMike Aizatsky2016-12-211-0/+5
| | | | llvm-svn: 290278
* [sancov] hash prefix results in huge merge files, use shorter prefixMike Aizatsky2016-12-212-21/+20
| | | | llvm-svn: 290277
* [AArch64] Remove a redundant check. NFC.Haicheng Wu2016-12-211-2/+1
| | | | | | | | The case AM.Scale == 0 is already handled by the code right above. Differential Revision: https://reviews.llvm.org/D28003 llvm-svn: 290275
* Add the ability for DWARFDie objects to get the parent DWARFDie.Greg Clayton2016-12-217-82/+209
| | | | | | | | | | | | In order for the llvm DWARF parser to be used in LLDB we will need to be able to get the parent of a DIE. This patch adds that functionality by changing the DWARFDebugInfoEntry class to store a depth field instead of a sibling index. Using a depth field allows us to easily calculate the sibling and the parent without increasing the size of DWARFDebugInfoEntry. I tested llvm-dsymutil on a debug version of clang where this fully parses DWARF in over 1200 .o files to verify there was no serious regression in performance. Added a full suite of unit tests to test this functionality. Differential Revision: https://reviews.llvm.org/D27995 llvm-svn: 290274
* cmake: Don't build llvm-config and tblgen concurrently in cross buildsJustin Bogner2016-12-211-1/+2
| | | | | | | | | | | | | This sets USES_TERMINAL for the native llvm-config build, so that it doesn't run at the same time as builds of other native tools (namely, tablegen). Without this, if you're very unlucky with the timing it's possible to be relinking libSupport as one of the tools is linking, causing a spurious failure. The tablegen build adopted USES_TERMINAL for this same reason in r280748. llvm-svn: 290271
* Update mailing list post URL and add libunwind referenceEd Maste2016-12-211-1/+2
| | | | | | | | | | | | | RTDyldMemoryManager.cpp describes the differing __register_frame API between libunwind and libgcc, with a mailing list posting URL. The original link was 404; replace it with what I believe is the intended post, as well as a reference to the "OS X" implementation in libunwind. Differential Revision: https://reviews.llvm.org/D27965 llvm-svn: 290269
* [X86][SSE] Improve lowering of vXi64 multiplies Simon Pilgrim2016-12-219-482/+422
| | | | | | | | | | | | | | | | | | | | | | As mentioned on PR30845, we were performing our vXi64 multiplication as: AloBlo = pmuludq(a, b); AloBhi = pmuludq(a, psrlqi(b, 32)); AhiBlo = pmuludq(psrlqi(a, 32), b); return AloBlo + psllqi(AloBhi, 32)+ psllqi(AhiBlo, 32); when we could avoid one of the upper shifts with: AloBlo = pmuludq(a, b); AloBhi = pmuludq(a, psrlqi(b, 32)); AhiBlo = pmuludq(psrlqi(a, 32), b); return AloBlo + psllqi(AloBhi + AhiBlo, 32); This matches the lowering on gcc/icc. Differential Revision: https://reviews.llvm.org/D27756 llvm-svn: 290267
* Revert "[InstCombine] New opportunities for FoldAndOfICmp and FoldXorOfICmp"David Majnemer2016-12-213-302/+2
| | | | | | This reverts commit r289813, it caused PR31449. llvm-svn: 290266
* AMDGPU/SI: Fix file headerTom Stellard2016-12-211-1/+1
| | | | llvm-svn: 290265
* TypeMetadataUtils: Simplify; spotted by Mehdi.Peter Collingbourne2016-12-211-2/+1
| | | | llvm-svn: 290264
* Add missing includes on Windows.Zachary Turner2016-12-212-0/+4
| | | | | | | Patch by Andrey Khalyavin Differential Revision: https://reviews.llvm.org/D27915 llvm-svn: 290263
* [LLParser] Parse vector GEP constant expression correctlyMichael Kuperstein2016-12-213-4/+24
| | | | | | | | | | | The constantexpr parsing was too constrained and rejected legal vector GEPs. This relaxes it to be similar to the ones for instruction parsing. This fixes PR30816. Differential Revision: https://reviews.llvm.org/D28013 llvm-svn: 290261
* [ConstantFolding] Fix vector GEPs harderMichael Kuperstein2016-12-212-3/+27
| | | | | | | | | | For vector GEPs, CastGEPIndices can end up in an infinite recursion, because we compare the vector type to the scalar pointer type, find them different, and then try to cast a type to itself. Differential Revision: https://reviews.llvm.org/D28009 llvm-svn: 290260
* [CostModel] Pass shuffle mask args with ArrayRef. NFCI.Simon Pilgrim2016-12-211-2/+2
| | | | llvm-svn: 290257
* revert first commit . removing empty line in X86.hMichael Zuckerman2016-12-211-1/+0
| | | | llvm-svn: 290255
* First commit adding new line to X86.hMichael Zuckerman2016-12-211-0/+1
| | | | llvm-svn: 290254
* Added a template for building target specific memory node in DAG.Elena Demikhovsky2016-12-2110-161/+445
| | | | | | | | | | I added API for creation a target specific memory node in DAG. Today, all memory nodes are common for all targets and their constructors are located in SelectionDAG.cpp. There are some cases in X86 where we need to create a special node - truncation-with-saturation store, float-to-half-store. In the current patch I added truncation-with-saturation nodes and I'm using them for intrinsics. In the future I plan to implement DAG lowering for truncation-with-saturation pattern. Differential Revision: https://reviews.llvm.org/D27899 llvm-svn: 290250
* [AMDGPU] Garbage collect dead code. NFCI.Davide Italiano2016-12-211-15/+0
| | | | llvm-svn: 290249
* [X86] Vectorcall Calling Convention - Adding CodeGen Complete SupportOren Ben Simhon2016-12-211-4/+4
| | | | | | Fixing a warning. llvm-svn: 290248
* [X86] Vectorcall Calling Convention - Adding CodeGen Complete SupportOren Ben Simhon2016-12-211-1/+1
| | | | | | Fixing failing test. llvm-svn: 290246
* [X86] Vectorcall Calling Convention - Adding CodeGen Complete SupportOren Ben Simhon2016-12-211-4/+4
| | | | | | Fixing build issues. llvm-svn: 290244
* [X86] Vectorcall Calling Convention - Adding CodeGen Complete SupportOren Ben Simhon2016-12-219-72/+471
| | | | | | | | | | | | | The vectorcall calling convention specifies that arguments to functions are to be passed in registers, when possible. vectorcall uses more registers for arguments than fastcall or the default x64 calling convention use. The vectorcall calling convention is only supported in native code on x86 and x64 processors that include Streaming SIMD Extensions 2 (SSE2) and above. The current implementation does not handle Homogeneous Vector Aggregates (HVAs) correctly and this review attempts to fix it. This aubmit also includes additional lit tests to cover better HVAs corner cases. Differential Revision: https://reviews.llvm.org/D27392 llvm-svn: 290240
* [LDist] Match behavior between invoking via optimization pipeline or opt ↵Adam Nemet2016-12-2118-61/+35
| | | | | | | | | | | | | | | | | | | | | | | | -loop-distribute In r267672, where the loop distribution pragma was introduced, I tried it hard to keep the old behavior for opt: when opt is invoked with -loop-distribute, it should distribute the loop (it's off by default when ran via the optimization pipeline). As MichaelZ has discovered this has the unintended consequence of breaking a very common developer work-flow to reproduce compilations using opt: First you print the pass pipeline of clang with -debug-pass=Arguments and then invoking opt with the returned arguments. clang -debug-pass will include -loop-distribute but the pass is invoked with default=off so nothing happens unless the loop carries the pragma. While through opt (default=on) we will try to distribute all loops. This changes opt's default to off as well to match clang. The tests are modified to explicitly enable the transformation. llvm-svn: 290235
* remove pretty-print test that requires debugSebastian Pop2016-12-211-5/+0
| | | | | | | There is no need to test the pretty printer. Remove the boggus test to make the build bots happy. llvm-svn: 290234
* [APFloat] Remove 'else' after return. NFCTim Shen2016-12-212-60/+56
| | | | | | | | | | Reviewers: kbarton, iteratee, hfinkel, echristo Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D27934 llvm-svn: 290232
* [Orc][RPC] Actually specialize SerializationTraits and RPCTypeName in the rightLang Hames2016-12-211-24/+40
| | | | | | | | namespace. r290226 was a think-o - just qualifying the name doesn't count. llvm-svn: 290230
* machine combiner: fix pretty printerSebastian Pop2016-12-214-12/+20
| | | | | | | | | | | we used to print UNKNOWN instructions when the instruction to be printer was not yet inserted in any BB: in that case the pretty printer would not be able to compute a TII as the instruction does not belong to any BB or function yet. This patch explicitly passes the TII to the pretty-printer. Differential Revision: https://reviews.llvm.org/D27645 llvm-svn: 290228
* [Orc][RPC] Specialize RPCTypeName and SerializationTraits in the right ↵Lang Hames2016-12-211-3/+3
| | | | | | namespace. llvm-svn: 290226
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