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* [IRCE] Use range-for; NFCSanjoy Das2016-08-131-5/+3
| | | | llvm-svn: 278606
* [ADT] Add a reserve() method to DenseSet as well as an insert() for R-valueMehdi Amini2016-08-132-1/+81
| | | | | | Recommit 278600 with some fixes to make the test more robust. llvm-svn: 278604
* Revert "[ADT] Add a reserve method to DenseSet as well as an insert() for ↵Mehdi Amini2016-08-132-72/+0
| | | | | | | | | R-value" This reverts commit r278600. The unittest does not pass on MSVC, there is an extra move. Investigating how to make it more robust. llvm-svn: 278603
* Limit DenseMap::setNumEntries input to 1<<31, in accordance with the 31 bits ↵Yaron Keren2016-08-131-2/+2
| | | | | | | | allocated to NumEntries. std::numeric_limits<int>::max() may be something else than 1<<31. llvm-svn: 278602
* Add missing REQUIRES in sancov/print_coverage_pcs.test: it requires aarch64 ↵Mehdi Amini2016-08-131-1/+1
| | | | | | as well now llvm-svn: 278601
* [ADT] Add a reserve method to DenseSet as well as an insert() for R-valueMehdi Amini2016-08-132-0/+72
| | | | llvm-svn: 278600
* [x86] add tests to show missed 64-bit immediate mergingSanjay Patel2016-08-131-0/+54
| | | | | | | Tests are slightly modified versions of those written by Sunita Marathe in D23391. llvm-svn: 278599
* Test commitAditya Kumar2016-08-131-2/+4
| | | | llvm-svn: 278598
* [X86] Add a check of isCommutable at the top of ↵Craig Topper2016-08-131-0/+3
| | | | | | | | X86InstrInfo::findCommutedOpIndices. Most callers don't check if the instruction is commutable before calling. This saves us the trouble of ending up in the default of the switch and having to determine if this is an FMA or not. llvm-svn: 278597
* [AVX-512] Add isCommutable to scalar FMA3 instructions.Craig Topper2016-08-131-5/+5
| | | | llvm-svn: 278596
* [AVX-512] Add commutable flags to 132 form FMA3 instructions.Craig Topper2016-08-131-3/+3
| | | | llvm-svn: 278595
* [X86] Remove patterns for (vzmovl (insert_subvector undef, ↵Craig Topper2016-08-131-11/+0
| | | | | | (scalar_to_vector))) as the (vzmovl VR256) pattern has higher priority. NFC llvm-svn: 278594
* [AVX-512] Remove an AddedComplexity that was prioritizing basic vzmovl ↵Craig Topper2016-08-132-13/+7
| | | | | | patterns over more complex ones that produce better code. llvm-svn: 278593
* [AVX-512] Add patterns to support VZEXT_MOVL from 512-bit vectors with ↵Craig Topper2016-08-135-1/+117
| | | | | | | | 64-bit and 32-bit elements. Fixes PR28961. llvm-svn: 278592
* [PM] Port LoopDataPrefetch to new pass managerTeresa Johnson2016-08-137-62/+136
| | | | | | | | | | | | | | | | Summary: Refactor the existing support into a LoopDataPrefetch implementation class and a LoopDataPrefetchLegacyPass class that invokes it. Add a new LoopDataPrefetchPass for the new pass manager that utilizes the LoopDataPrefetch implementation class. Reviewers: mehdi_amini Subscribers: sanjoy, mzolotukhin, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D23483 llvm-svn: 278591
* AMDGPU: Fix not estimating MBB operand sizes correctlyMatt Arsenault2016-08-132-2/+26
| | | | llvm-svn: 278590
* AMDGPU: Fix missing test for addressing mode with odd offsetsMatt Arsenault2016-08-132-5/+32
| | | | | | Add test if the constant offset looks unaligned. llvm-svn: 278589
* AMDGPU/R600: Remove macrosMatt Arsenault2016-08-135-36/+33
| | | | llvm-svn: 278588
* Fix more dereferenced end() iterators after r278532Hans Wennborg2016-08-135-8/+16
| | | | llvm-svn: 278587
* Constify ValueTracking. NFC.Pete Cooper2016-08-132-121/+166
| | | | | | | Almost all of the method here are only analysing Value's as opposed to mutating them. Mark all of the easy ones as const. llvm-svn: 278585
* [IndVars] Ignore (s|z)exts that don't extend the induction variableSanjoy Das2016-08-132-0/+28
| | | | | | | | | | | | | | | | | | `IVVisitor::visitCast` used to have the invariant that if the instruction it was passed was a sext or zext instruction, the result of the instruction would be wider than the induction variable. This is no longer true after rL275037, so this change teaches `IndVarSimplify` s implementation of `IVVisitor::visitCast` to work with the relaxed invariant. A corresponding change to SimplifyIndVar to preserve the said invariant after rL275037 would also work, but given how `IVVisitor::visitCast` is spelled (no indication of said invariant), I figured the current fix is cleaner. Fixes PR28935. llvm-svn: 278584
* Fix some Clang-tidy modernize-use-using and Include What You Use warnings.Eugene Zelenko2016-08-136-55/+121
| | | | | | Differential revision: https://reviews.llvm.org/D23478 llvm-svn: 278583
* [libFuzzer] mention one more trophie in LLVMKostya Serebryany2016-08-131-1/+1
| | | | llvm-svn: 278582
* [LSV] Use a set rather than an ArraySlice at the end of ↵Justin Lebar2016-08-131-6/+5
| | | | | | | | | | | | | | getVectorizablePrefix. NFC Summary: This avoids a small O(n^2) loop. Reviewers: asbirlea Subscribers: mzolotukhin, llvm-commits, arsenm Differential Revision: https://reviews.llvm.org/D23473 llvm-svn: 278581
* [LSV] Use OrderedBasicBlock instead of rolling it ourselves. NFCJustin Lebar2016-08-131-23/+21
| | | | | | | | | | | | | | | | | | | Summary: In getVectorizablePrefix, this is less efficient (because we have to iterate over the BB twice), but boy is it simpler. Given how much trouble we've had here, I think the simplicity gain is worthwhile. In reorder(), this is actually more efficient, as DominatorTree::dominates iterates over the BB from the beginning when the two instructions are in the same BB. Reviewers: asbirlea Subscribers: arsenm, llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D23472 llvm-svn: 278580
* Minor comment fix ("generate" --> "generates").Justin Lebar2016-08-121-1/+1
| | | | llvm-svn: 278578
* X86: Fix another dereferenced end() iterator after r278532Hans Wennborg2016-08-121-1/+1
| | | | llvm-svn: 278577
* [WebAssembly] Re-enable disabled debug value testDominic Chen2016-08-121-1/+0
| | | | | | | | | | | | | | | Summary: This test was resulting in asan/valgrind failures due to undefined DWARF register mappings for WebAssembly, and was disabled in r278495. These have been resolved. Reviewers: sunfish, dschuff Subscribers: bkramer, llvm-commits, jfb Differential Revision: https://reviews.llvm.org/D23459 llvm-svn: 278576
* Reapply [BranchFolding] Restrict tail merging loop blocks after MBPHaicheng Wu2016-08-123-10/+116
| | | | | | | | | Fixed a bug in the test case. To fix PR28104, this patch restricts tail merging to blocks that belong to the same loop after MBP. llvm-svn: 278575
* Avoid accessing LLVM/DWARF register mappings if undefinedDominic Chen2016-08-122-0/+14
| | | | | | | | | | | | | | | | | Summary: If the backend does not define LLVM/DWARF register mappings, the associated variables are undefined since the map initializer is called by auto-generated TableGen routines. This patch initializes the pointers and sizes to nullptr and zero, respectively, and checks that they are valid before searching for a mapping. Reviewers: grosbach, dschuff Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23458 llvm-svn: 278574
* [LoopVectorize] Detect loops in the innermost loop before creating ↵Tim Shen2016-08-122-6/+158
| | | | | | | | | | | | | InnerLoopVectorizer InnerLoopVectorizer shouldn't handle a loop with cycles inside the loop body, even if that cycle isn't a natural loop. Fixes PR28541. Differential Revision: https://reviews.llvm.org/D22952 llvm-svn: 278573
* X86: Stop dereferencing end() in X86FrameLowering::emitEpilogueDuncan P. N. Exon Smith2016-08-121-5/+7
| | | | | | | | | | | | | On a Windows build of Chromium, r278532 (up to r278539) X86FrameLowering::emitEpilogue because it wasn't wary enough of the return of MachineBasicBlock::getFirstTerminator. Guard all the uses here. Note that r278532 *looks* like an NFC commit (just an API change), but it removes a couple of layers of abstraction and is probably causing optimization differences in MSVC. llvm-svn: 278572
* [Inliner] Don't treat inalloca allocas as staticReid Kleckner2016-08-122-3/+73
| | | | | | | | | They aren't static, and moving them to the entry block across something else will only result in tears. Root cause of http://crbug.com/636558. llvm-svn: 278571
* Add support to paternmatch for simple const Value cases.Pete Cooper2016-08-122-3/+30
| | | | | | | | | | | | | Pattern match has some paths which can operate on constant instructions, but not all. This adds a version of m_value() to return const Value* and changes ICmp matching to use auto so that it can match both constant and mutable instructions. Tests also included for both mutable and constant ICmpInst matching. This will be used in a future commit to constify ValueTracking.cpp. llvm-svn: 278570
* [ADT] Add filter_iterator for filtering elementsTim Shen2016-08-123-9/+162
| | | | | | Differential Revision: https://reviews.llvm.org/D22951 llvm-svn: 278569
* [NVPTX] Use untyped (.b) integer registers in PTX.Artem Belevich2016-08-122-3/+90
| | | | | | | | | | | | This bring LLVM-generated PTX closer to what nvcc generates and avoids triggering issues in ptxas. For instance, ptxas does not accept .s16 (or .u16) registers as operands for .fp16 instructions. Differential Revision: https://reviews.llvm.org/D23460 llvm-svn: 278568
* gold: add a cast to appease std::max NFCSaleem Abdulrasool2016-08-121-1/+2
| | | | llvm-svn: 278567
* [PM] BitcodeWriterPass should derive from PassInfoMixinTeresa Johnson2016-08-121-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: The BitcodeWriterPass was ported a couple years ago, and predates the PassInfoMixin. Make BitcodeWriterPass from that base class. Should BitcodeWriterPass be added to the PassRegistry.def file? It seems like that is only for passes that can be added arbitrarily, e.g. via the -passes flag to the opt tool. Whereas the bitcode writer is added specially based on the output type (and requires an output stream and other parameters). For now I have left it out of the PassRegistry, but let me know if it should go there. Finally, I was considering an NFC change of the legacy WriteBitcodePass to BitcodeWriterLegacyPass to make its usage clearer and more consistent with other legacy passes. WDYT? Reviewers: mehdi_amini Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23465 llvm-svn: 278566
* Fixed typo.David L Kreitzer2016-08-121-1/+1
| | | | llvm-svn: 278565
* [Hexagon] Cleanup and standardize vector load/store pseudo instructionsKrzysztof Parzyszek2016-08-123-243/+187
| | | | | | | | | | | | | | | | | | | | Remove the following single-vector load/store pseudo instructions, use real instructions instead: LDriv_pseudo_V6 STriv_pseudo_V6 LDriv_pseudo_V6_128B STriv_pseudo_V6_128B LDrivv_indexed STrivv_indexed LDrivv_indexed_128B STrivv_indexed_128B Rename the double-vector load/store pseudo instructions, add unaligned counterparts: -- old -- -- new -- -- unaligned -- LDrivv_pseudo_V6 PS_vloadrw_io PS_vloadrwu_io LDrivv_pseudo_V6_128B PS_vloadrw_io_128B PS_vloadrwu_io_128B STrivv_pseudo_V6 PS_vstorerw_io PS_vstorerwu_io STrivv_pseudo_V6_128B PS_vstorerw_io_128 PS_vstorerwu_io_128 llvm-svn: 278564
* [libFuzzer] fix typo in docsKostya Serebryany2016-08-121-1/+1
| | | | llvm-svn: 278563
* [AArch64LoadStoreOptimizer] Check aliasing correctly when creating paired ↵Eli Friedman2016-08-122-1/+51
| | | | | | | | | | loads/stores. The existing code accidentally skipped the aliasing check in edge cases. Differential revision: https://reviews.llvm.org/D23372 llvm-svn: 278562
* [AArch64] Registering default MCInstrAnalysisMike Aizatsky2016-08-123-0/+12
| | | | | | | | | | | | Even in this form it is useful: it can detect branch instructions. https://github.com/google/sanitizers/issues/706 Subscribers: aemerson, rengolin Differential Revision: https://reviews.llvm.org/D23426 llvm-svn: 278560
* [AArch64LoadStoreOpt] Handle offsets correctly for post-indexed paired loads.Eli Friedman2016-08-122-6/+107
| | | | | | | | Trunk would try to create something like "stp x9, x8, [x0], #512", which isn't actually a valid instruction. Differential revision: https://reviews.llvm.org/D23368 llvm-svn: 278559
* Remove autoconf references from LICENSE.TXTChris Bieneman2016-08-121-2/+0
| | | | | | Since we don't actually have the autoconf subdirectories anymore, we don't need this reference here. llvm-svn: 278558
* Next set of additional error checks for invalid Mach-O files.Kevin Enderby2016-08-1213-26/+135
| | | | | | | | | | This contains the two missing checks for LC_SEGMENT load command fields. And checks for the Mach-O sections fields that would make them invalid. With the new checks, some of the existing malformed file checks now trips one of these instead of the issue it was having before so those tests were adjusted. llvm-svn: 278557
* [sancov] test file cleanupMike Aizatsky2016-08-121-1/+0
| | | | llvm-svn: 278556
* [sancov] MachO indirect symbols support.Mike Aizatsky2016-08-123-8/+80
| | | | | | Differential Revision: https://reviews.llvm.org/D23338 llvm-svn: 278551
* [PPC] Memoize getValueBits. NFC.Tim Shen2016-08-121-35/+49
| | | | | | | | | | | | Summary: It triggers exponential behavior when the DAG has many branches. Reviewers: hfinkel, kbarton Subscribers: iteratee, nemanjai, echristo Differential Revision: https://reviews.llvm.org/D23428 llvm-svn: 278548
* [WebAssembly] Plug MachineMemOperand leaks.Benjamin Kramer2016-08-121-6/+6
| | | | llvm-svn: 278545
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