summaryrefslogtreecommitdiffstats
path: root/llvm
Commit message (Collapse)AuthorAgeFilesLines
* Reserve space for the eventual filling of the vector. This gives a small ↵Bill Wendling2012-04-031-4/+3
| | | | | | speedup. llvm-svn: 153949
* Add an additional testcase which checks ops with multiple users.Nadav Rotem2012-04-031-0/+12
| | | | llvm-svn: 153939
* Make PPCCompilationCallbackC function to be static, so there will be no need ↵Anton Korobeynikov2012-04-031-3/+5
| | | | | | | | to issue call via PLT when LLVM is built as shared library. This mimics the X86 backend towards the approach. llvm-svn: 153938
* Tidy up spacing in some tablegen outputs.Craig Topper2012-04-032-11/+9
| | | | llvm-svn: 153937
* Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.Craig Topper2012-04-039-41/+832
| | | | llvm-svn: 153935
* Reformatting. No functionality change.Bill Wendling2012-04-031-18/+19
| | | | llvm-svn: 153928
* As Eric pointed out, even a Debug build should be equal. Leave the flag that ↵Bill Wendling2012-04-031-10/+8
| | | | | | can turn off comparisons though. llvm-svn: 153927
* Revert r153924. Delete test/MC/Disassembler/Mips and ↵Akira Hatanaka2012-04-0312-0/+0
| | | | | | lib/Target/Mips/Disassembler. llvm-svn: 153926
* Revert r153924. There were buildbot failures.Akira Hatanaka2012-04-0321-2967/+104
| | | | llvm-svn: 153925
* MIPS disassembler support.Akira Hatanaka2012-04-0321-104/+2967
| | | | | | Patch by Vladimir Medic. llvm-svn: 153924
* Cleanup set_union usage. The same thing but a bit cleaner now.Andrew Trick2012-04-031-1/+1
| | | | llvm-svn: 153922
* Use std::set_union instead of nasty custom code.Andrew Trick2012-04-031-13/+3
| | | | | | | I just noticed Jakob's examples of the proper application of std::set... routines. llvm-svn: 153918
* Add a line number for the scope of the function (starting at the firstEric Christopher2012-04-036-5/+29
| | | | | | | | | | brace) so that we get more accurate line number information about the declaration of a given function and the line where the function first starts. Part of rdar://11026482 llvm-svn: 153916
* Fixes to r153903. Added missing explanation of behaviour when the ↵Pete Cooper2012-04-032-5/+10
| | | | | | VirtRegMap is NULL. Also changed it in this case to just avoid updating the map, but live ranges or intervals will still get updated and created llvm-svn: 153914
* Compare the .o files only for release builds. Add an option to bypass the ↵Bill Wendling2012-04-021-16/+26
| | | | | | comparison altogether. llvm-svn: 153909
* Moved LiveRangeEdit.h so that it can be called from other parts of the ↵Pete Cooper2012-04-029-8/+8
| | | | | | backend, not just libCodeGen llvm-svn: 153906
* Make dominatedBySlowTreeWalk private and assert cases handled by the caller.Rafael Espindola2012-04-021-21/+12
| | | | llvm-svn: 153905
* Allocate virtual registers in ascending order.Jakob Stoklund Olesen2012-04-026-17/+38
| | | | | | | | | This is just the fallback tie-breaker ordering, the main allocation order is still descending size. Patch by Shamil Kurmangaleev! llvm-svn: 153904
* Refactored the LiveRangeEdit interface so that MachineFunction, ↵Pete Cooper2012-04-028-93/+76
| | | | | | TargetInstrInfo, MachineRegisterInfo, LiveIntervals, and VirtRegMap are all passed into the constructor and stored as members instead of passed in to each method. llvm-svn: 153903
* Add an option to turn off the expensive GVN load PRE part of GVN.Bill Wendling2012-04-023-6/+13
| | | | llvm-svn: 153902
* Add predicates for checking whether targets have free FNEG and FABS ↵Owen Anderson2012-04-022-3/+17
| | | | | | operations, and prevent the DAGCombiner from turning them into bitwise operations if they do. llvm-svn: 153901
* During two-address lowering, rescheduling an instruction does not untieLang Hames2012-04-022-2/+26
| | | | | | | operands. Make TryInstructionTransform return false to reflect this. Fixes PR11861. llvm-svn: 153892
* No need to run llvm-as.Rafael Espindola2012-04-021-1/+1
| | | | llvm-svn: 153890
* Initial 64 bit direct object support.Akira Hatanaka2012-04-026-29/+82
| | | | | | | | | | | This patch allows llvm to recognize that a 64 bit object file is being produced and that the subsequently generated ELF header has the correct information. The test case checks for both big and little endian flavors. Patch by Jack Carter. llvm-svn: 153889
* The binutils for the IBM BG/P are too old to support CFI.Hal Finkel2012-04-022-0/+6
| | | | llvm-svn: 153886
* Add triple support for the IBM BG/P and BG/Q supercomputers.Hal Finkel2012-04-023-2/+29
| | | | llvm-svn: 153882
* Turn on the accelerator tables for Darwin.Eric Christopher2012-04-021-0/+6
| | | | llvm-svn: 153880
* Fast fix for PR12343:Stepan Dyatkovskiy2012-04-022-4/+75
| | | | | | | | | | http://llvm.org/bugs/show_bug.cgi?id=12343 We have not trivial way for splitting edges that are goes from indirect branch. We can do it with some tricks, but it should be additionally discussed. And it is still dangerous due to difficulty of indirect branches controlling. Fix forbids this case for unswitching. llvm-svn: 153879
* Implement the SVR4 byval alignment for aggregates. Fixing a FIXME.Roman Divacky2012-04-021-1/+10
| | | | llvm-svn: 153876
* Second part for the 153874 oneSilviu Baranga2012-04-021-3/+3
| | | | llvm-svn: 153875
* Added fix in TableGen instruction decoder generation. The decoder now breaks ↵Silviu Baranga2012-04-021-0/+15
| | | | | | for every leaf node. llvm-svn: 153874
* Add missing 'd'.Rafael Espindola2012-04-021-1/+1
| | | | llvm-svn: 153872
* Hack the hack. If we have a situation where an ASM object is defined but isn'tBill Wendling2012-04-022-23/+17
| | | | | | | | | | reflected in the LLVM IR (as a declare or something), then treat it like a data object. N.B. This isn't 100% correct. The ASM parser should supply more information so that we know what type of object it is, and what attributes it should have. llvm-svn: 153870
* Emit the asm writer's mnemonic table with SequenceToOffsetTable.Benjamin Kramer2012-04-021-6/+21
| | | | | | This way we can get AVX v-prefixed instructions tail merged with the normal insns. llvm-svn: 153869
* Move getOpcodeName from the various target InstPrinters into the superclass ↵Benjamin Kramer2012-04-0214-31/+3
| | | | | | | | MCInstPrinter. All implementations used the same code. llvm-svn: 153866
* Reorder fields in MatchEntry and OperandMatchEntry to reduce padding. A bit ↵Craig Topper2012-04-021-24/+25
| | | | | | tricky due to the target specific sizes for some of the fields so the ordering is only optimal for the targets in the tree. llvm-svn: 153865
* Optimizing swizzles of complex shuffles may generate additional complex ↵Nadav Rotem2012-04-022-1/+26
| | | | | | | | | shuffles. Do not try to optimize swizzles of shuffles if the source shuffle has more than a single user, except when the source shuffle is also a swizzle. llvm-svn: 153864
* Remove getInstructionName from MCInstPrinter implementations in favor of ↵Craig Topper2012-04-0215-74/+12
| | | | | | using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations. llvm-svn: 153863
* Fix CXXFLAGS for huge_val.m4.Eric Christopher2012-04-022-2/+2
| | | | | | Patch by Jeremy Huddleston! llvm-svn: 153862
* Make MCInstrInfo available to the MCInstPrinter. This will be used to remove ↵Craig Topper2012-04-0227-41/+89
| | | | | | getInstructionName and the static data it contains since the same tables are already in MCInstrInfo. llvm-svn: 153860
* It could come about that we parse the inline ASM before we get a potentialBill Wendling2012-04-022-0/+27
| | | | | | | definition for it. In that case, we want to wait for the potential definition before we create a symbol for it. llvm-svn: 153859
* Use SequenceToOffsetTable to generate instruction name table for AsmWriter.Craig Topper2012-04-021-25/+27
| | | | llvm-svn: 153857
* Start cleaning up the InlineCost class. This switches to sentinel valuesChandler Carruth2012-04-011-25/+20
| | | | | | | | | | | rather than a bitfield, a great suggestion by Chris during code review. There is still quite a bit of cruft in the interface, but that requires sorting out some awkward uses of the cost inside the actual inliner. No functionality changed intended here. llvm-svn: 153853
* Fix some 80-col. violations I introduced with the A2 PPC64 core.Hal Finkel2012-04-012-63/+126
| | | | llvm-svn: 153852
* Enable prefetch generation on PPC64.Hal Finkel2012-04-013-0/+21
| | | | llvm-svn: 153851
* Add LdStSTD* itin. for the PPC64 A2 core.Hal Finkel2012-04-011-0/+20
| | | | llvm-svn: 153850
* This commit contains a few changes that had to go in together.Nadav Rotem2012-04-018-22/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) (and also scalar_to_vector). 2. Xor/and/or are indifferent to the swizzle operation (shuffle of one src). Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A, B)) 3. Optimize swizzles of shuffles: shuff(shuff(x, y), undef) -> shuff(x, y). 4. Fix an X86ISelLowering optimization which was very bitcast-sensitive. Code which was previously compiled to this: movd (%rsi), %xmm0 movdqa .LCPI0_0(%rip), %xmm2 pshufb %xmm2, %xmm0 movd (%rdi), %xmm1 pshufb %xmm2, %xmm1 pxor %xmm0, %xmm1 pshufb .LCPI0_1(%rip), %xmm1 movd %xmm1, (%rdi) ret Now compiles to this: movl (%rsi), %eax xorl %eax, (%rdi) ret llvm-svn: 153848
* Fix typo.Lang Hames2012-04-011-1/+1
| | | | llvm-svn: 153846
* Set the default PPC node scheduling preference to ILP (for the embedded cores).Hal Finkel2012-04-012-0/+10
| | | | | | | The 440 and A2 cores have detailed itineraries, and this allows them to be fully used to maximize throughput. llvm-svn: 153845
* Add ppc440 itin. entries for LdStSTD*Hal Finkel2012-04-011-0/+20
| | | | llvm-svn: 153844
OpenPOWER on IntegriCloud