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* [SystemZ] Rework processor feature definitions and add -mcpu=archX supportUlrich Weigand2016-10-3113-88/+198
| | | | | | | | | | | | | | | | | | | This patch implements two changes: - Move processor feature definition into a new file SystemZFeatures.td, and provide explicit lists of supported and unsupported features for each level of the z/Architecture. This allows specifying unsupported features in the scheduler definition files for each processor. - Add optional aliases for the -mcpu processor names according to the level of the z/Architecture, for compatibility with other compilers on the platform. The supported aliases are: -mcpu=arch8 equals -mcpu=z10 -mcpu=arch9 equals -mcpu=z196 -mcpu=arch10 equals -mcpu=zEC12 -mcpu=arch11 equals -mcpu=z13 llvm-svn: 285577
* [SystemZ] Guard LEFR/LFER with FeatureVectorUlrich Weigand2016-10-311-5/+7
| | | | | | | | | | | The LEFR/LFER pseudos are aliases for vector instructions and should therefore be guared by FeatureVector. If they aren't, the TableGen scheduler definition checking might complain that there is no data for those pseudos for pre-z13 machines. No functional change intended. llvm-svn: 285576
* [SystemZ] Correctly diagnose missing features in AsmParserUlrich Weigand2016-10-314-483/+489
| | | | | | | | | | | | | | | | | Currently, when using an instruction that is not supported on the currently selected architecture, the LLVM assembler is likely to diagnose an "invalid operand" instead of a "missing feature". This is because many operands require a custom parser in order to be processed correctly, and if an instruction is not available according to the current feature set, the generated parser code will also not detect the associated custom operand parsers. Fixed by temporarily enabling all features while parsing operands. The missing features will then be correctly detected when actually parsing the instruction itself. llvm-svn: 285575
* [SystemZ] Fix encoding of MVCK and .insn ssUlrich Weigand2016-10-3112-107/+259
| | | | | | | | | | | | | | | | | | | | LLVM currently treats the first operand of MVCK as if it were a regular base+index+displacement address. However, it is in fact a base+displacement combined with a length register field. While the two might look syntactically similar, there are two semantic differences: - %r0 is a valid length register, even though it cannot be used as an index register. - In an expression with just a single register like 0(%rX), the register is treated as base with normal addresses, while it is treated as the length register (with an empty base) for MVCK. Fixed by adding a new operand parser class BDRAddr and reworking the assembler parser to distinguish between address + length register operands and regular addresses. llvm-svn: 285574
* Second attempt at r285517.Dorit Nuzman2016-10-317-14/+261
| | | | llvm-svn: 285568
* [SystemZ] Model 2 VBU units (not 1) in SystemZScheduleZ13.td.Jonas Paulsson2016-10-311-1/+1
| | | | | | | NFC. Review: Ulrich Weigand. llvm-svn: 285566
* Improved cost model for FDIV and FSQRT, by Andrew TischenkoAlexey Bataev2016-10-312-84/+156
| | | | | | | | | | There is a bug describing poor cost model for floating point operations: Bug 29083 - [X86][SSE] Improve costs for floating point operations. This patch is the second one in series of patches dealing with cost model. Differential Revision: https://reviews.llvm.org/D25722 llvm-svn: 285564
* Add triple to test so it does not fail on windows.Manuel Klimek2016-10-311-1/+1
| | | | llvm-svn: 285560
* Delete .s file that did not test anything, and check in test that works.Manuel Klimek2016-10-312-20/+27
| | | | | | | In D26098, Davide Italiano submitted a .s file instead of the .ll file that was the last stage of the review. llvm-svn: 285559
* Add getOffset to ELFSectionRefEugene Leviant2016-10-311-0/+11
| | | | | | Differential revision: https://reviews.llvm.org/D26074 llvm-svn: 285558
* [AVX-512] Add missing patterns for selecting masked vector extracts that ↵Craig Topper2016-10-312-9/+263
| | | | | | started from shuffles. llvm-svn: 285546
* Make a test case more rigorous; NFCSanjoy Das2016-10-311-21/+8
| | | | llvm-svn: 285536
* [SCEV] Try to order n-ary expressions in CompareValueComplexitySanjoy Das2016-10-312-30/+72
| | | | llvm-svn: 285535
* [SCEV] Reduce boilerplate in unit testsSanjoy Das2016-10-311-32/+27
| | | | llvm-svn: 285534
* [SCEV] In CompareValueComplexity, order global values by their nameSanjoy Das2016-10-302-1/+41
| | | | llvm-svn: 285529
* [SCEV] Use auto for consistency with an upcoming change; NFCSanjoy Das2016-10-301-4/+4
| | | | llvm-svn: 285528
* Clean up test a little bit; NFCSanjoy Das2016-10-301-16/+16
| | | | llvm-svn: 285527
* [DAG] x | x --> xSanjay Patel2016-10-302-2/+4
| | | | llvm-svn: 285522
* [DAG] x & x --> xSanjay Patel2016-10-302-2/+4
| | | | llvm-svn: 285521
* [x86] add tests for basic logic op foldsSanjay Patel2016-10-302-0/+37
| | | | llvm-svn: 285520
* Revert r285517 due to build failures.Dorit Nuzman2016-10-307-255/+4
| | | | llvm-svn: 285518
* [LoopVectorize] Make interleaved-accesses analysis less conservative aboutDorit Nuzman2016-10-307-4/+255
| | | | | | | | | | | | | | | | | | | | | possible pointer-wrap-around concerns, in some cases. Before this patch, collectConstStridedAccesses (part of interleaved-accesses analysis) called getPtrStride with [Assume=false, ShouldCheckWrap=true] when examining all candidate pointers. This is too conservative. Instead, this patch makes collectConstStridedAccesses use an optimistic approach, calling getPtrStride with [Assume=true, ShouldCheckWrap=false], and then, once the candidate interleave groups have been formed, revisits the pointer-wrapping analysis but only where it matters: namely, in groups that have gaps, and where the gaps are not at the very end of the group (in which case the loop is peeled). This second time getPtrStride is called with [Assume=false, ShouldCheckWrap=true], but this could further be improved to using Assume=true, once we also add the logic to track that we are not going to meet the scev runtime checks threshold. Differential Revision: https://reviews.llvm.org/D25276 llvm-svn: 285517
* [X86] Use intrinsics table for PMADDUBSW and PMADDWD so that we can use the ↵Craig Topper2016-10-303-86/+57
| | | | | | | | legacy intrinsics to select EVEX encoded instructions when available. This removes a couple tablegen classes that become unused after this change. Another class gained an additional parameter to allow PMADDUBSW to specify a different result type from its input type. llvm-svn: 285515
* [Polly] Remove the unused POLLY_LINK_LIBS for linking polly intoHongbin Zheng2016-10-302-10/+0
| | | | | | | | tools Differential Revision: https://reviews.llvm.org/D25861 llvm-svn: 285514
* [ThinLTO] Use per-summary flag to prevent exporting locals used in inline asmTeresa Johnson2016-10-304-59/+34
| | | | | | | | | | | | | | | | | | | | | Summary: Instead of using the workaround of suppressing the entire index for modules that call inline asm that may reference locals, use the NoRename flag on the summary for any locals in the llvm.used set, and add a reference edge from any functions containing inline asm. This avoids issues from having no summaries despite the module defining global values, which was preventing more aggressive index-based optimization. It will be followed by a subsequent patch to make a similar fix for local references in module level asm (to fix PR30610). Reviewers: mehdi_amini Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26121 llvm-svn: 285513
* [ThinLTO] Correctly resolve linkonce when importing aliaseeTeresa Johnson2016-10-306-23/+107
| | | | | | | | | | | | | | | | | | | Summary: When we have an aliasee that is linkonce, while we can't convert the non-prevailing copies to available_externally, we still need to convert the prevailing copy to weak. If a reference to the aliasee is exported, not converting a copy to weak will result in undefined references when the linkonce is removed in its original module. Add a new test and update existing tests. Reviewers: mehdi_amini Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26076 llvm-svn: 285512
* [X86] Don't use loadv2i64 on SSE version of PMULHRSW. Use memopv2i64 instead.Craig Topper2016-10-301-1/+1
| | | | | | This bug was introduced in r285501. llvm-svn: 285510
* NativeFormatting.cpp: Fix build for mingw. Where would writePadding() be?NAKAMURA Takumi2016-10-291-1/+0
| | | | llvm-svn: 285509
* [ThinLTO] Rename doPromoteLocalToGlobal to shouldPromoteLocalToGlobal (NFC)Teresa Johnson2016-10-292-4/+4
| | | | | | Rename as suggested in code review for D26063. llvm-svn: 285508
* [ThinLTO] Use NoPromote flag in summary during promotionTeresa Johnson2016-10-292-17/+25
| | | | | | | | | | | | | | | | Summary: Replace the check of whether a GV has a section with the flag check in the summary. This is in preparation for using the NoPromote flag to convey other situations when we can't promote (e.g. locals used in inline asm). Reviewers: mehdi_amini Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26063 llvm-svn: 285507
* IR: Remove a no longer needed assert.Peter Collingbourne2016-10-291-5/+0
| | | | | | | This assert was checking for a miscompile in a version of GCC that we no longer support. llvm-svn: 285506
* [X86] Use intrinsics table for VPMULHRSW intrincis so that the legacy ↵Craig Topper2016-10-293-12/+13
| | | | | | | | intrinsics can select EVEX encoded instructions when available. This requires a minor rename of the instructions due to the use of different tablegen classes and how the names are concatenated. llvm-svn: 285501
* [ValueTracking] recognize more variants of smin/smaxSanjay Patel2016-10-294-49/+33
| | | | | | | | | | | | | Try harder to detect obfuscated min/max patterns: the initial pattern was added with D9352 / rL236202. There was a bug fix for PR27137 at rL264996, but I think we can do better by folding the corresponding smax pattern and commuted variants. The codegen tests demonstrate the effect of ValueTracking on the backend via SelectionDAGBuilder. We can't expose these differences minimally in IR because we don't have smin/smax intrinsics for IR. Differential Revision: https://reviews.llvm.org/D26091 llvm-svn: 285499
* [x86] add tests for smin/smax matchSelPattern (D26091)Sanjay Patel2016-10-292-59/+127
| | | | llvm-svn: 285498
* [InstCombine] re-use bitcasted compare operands in selects (PR28001)Sanjay Patel2016-10-292-9/+56
| | | | | | | | | | | These mixed bitcast patterns show up with SSE/AVX intrinsics because we bitcast function parameters to <2 x i64>. The bitcasts obfuscate the expected min/max forms as shown in PR28001: https://llvm.org/bugs/show_bug.cgi?id=28001#c6 Differential Revision: https://reviews.llvm.org/D25943 llvm-svn: 285495
* [DAGCombiner] (REAPPLIED) Add vector demanded elements support to ↵Simon Pilgrim2016-10-294-59/+137
| | | | | | | | | | | | | | | | | | | | computeKnownBits Currently computeKnownBits returns the common known zero/one bits for all elements of vector data, when we may only be interested in one/some of the elements. This patch adds a DemandedElts argument that allows us to specify the elements we actually care about. The original computeKnownBits implementation calls with a DemandedElts demanding all elements to match current behaviour. Scalar types set this to 1. The approach was found to be easier than trying to add a per-element known bits solution, for a similar usefulness given the combines where computeKnownBits is typically used. I've only added support for a few opcodes so far (the ones that have proven straightforward to test), all others will default to demanding all elements but can be updated in due course. DemandedElts support could similarly be added to computeKnownBitsForTargetNode in a future commit. This looked like this had caused compile time regressions on some buildbots (and was reverted in rL285381), but appears to have just been a harmless bystander! Differential Revision: https://reviews.llvm.org/D25691 llvm-svn: 285494
* Fixed FMA + FNEG combine.Elena Demikhovsky2016-10-292-3/+119
| | | | | | | | Masked form of FMA should be omitted in this optimization. Differential Revision: https://reviews.llvm.org/D25984 llvm-svn: 285492
* AMDGPU: Use 1/2pi inline imm on VIMatt Arsenault2016-10-299-24/+113
| | | | | | I'm guessing at how it is supposed to be printed llvm-svn: 285490
* AArch64DeadRegisterDefinitionsPass: Cleanup; NFCMatthias Braun2016-10-291-54/+53
| | | | | | | | | | | - Fix doxygen file comment - reduce indentation in loop - Factor out some common subexpressions - Move independent helper function out of class - Fix Changed flag (this is not strictly NFC but a bugfix, but the flag seems ignored anyway) llvm-svn: 285488
* Define calculateDbgStreamSize for consistency.Rui Ueyama2016-10-292-1/+6
| | | | llvm-svn: 285487
* [APFloat] Remove the redundent function body of uninitialized ctor, which ↵Tim Shen2016-10-291-4/+1
| | | | | | should be done in r285468 llvm-svn: 285486
* Resubmit "Add support for advanced number formatting."Zachary Turner2016-10-295-104/+369
| | | | | | | | | | | | | This resubmits r284436 and r284437, which were reverted in r284462 as they were breaking the AArch64 buildbot. The breakage on AArch64 turned out to be a miscompile which is still not fixed, but is actively tracked at llvm.org/pr30748. This resubmission re-writes the code in a way so as to make the miscompile not happen. llvm-svn: 285483
* Do not print out Flags field twice.Rui Ueyama2016-10-282-11/+26
| | | | llvm-svn: 285481
* [DAGCombiner] Fix a crash visiting `AND` nodes.Davide Italiano2016-10-282-1/+26
| | | | | | | | | | Instead of asserting that the shift count is != 0 we just bail out as it's not profitable trying to optimize a node which will be removed anyway. Differential Revision: https://reviews.llvm.org/D26098 llvm-svn: 285480
* AMDGPU/SI: Don't use non-0 waitcnt values when waiting on Flat instructionsTom Stellard2016-10-284-2/+86
| | | | | | | | | | | | | | Summary: Flat instruction can return out of order, so we need always need to wait for all the outstanding flat operations. Reviewers: tony-tye, arsenm Subscribers: kzhuravl, wdng, nhaehnle, llvm-commits, yaxunl Differential Revision: https://reviews.llvm.org/D25998 llvm-svn: 285479
* AMDGPU: Fix instruction flags for s_endpgmMatt Arsenault2016-10-281-2/+1
| | | | | | | Set isReturn, remove hasSideEffects. Also remove hasCtrlDep, I'm not really sure what that does. llvm-svn: 285476
* Refactor DW_LNE_* into Dwarf.defAdrian Prantl2016-10-283-22/+29
| | | | llvm-svn: 285475
* Refactor DW_LNS_* into Dwarf.defAdrian Prantl2016-10-283-34/+37
| | | | llvm-svn: 285474
* Refactor DW_APPLE_PROPERTY_* into Dwarf.defAdrian Prantl2016-10-283-54/+40
| | | | llvm-svn: 285473
* Refactor DW_CFA_* into Dwarf.defAdrian Prantl2016-10-283-68/+52
| | | | llvm-svn: 285472
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