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* ARM cost model: Add cost for gather/scatherArnold Schwaighofer2013-07-122-0/+97
| | | | | | | | | | Fixes a 35% degradation compared to unvectorized code in MiBench/automotive-susan and an equally serious regression on a private image processing benchmark. radar://14351991 llvm-svn: 186188
* TargetTransformInfo: address calculation parameter for gather/scatherArnold Schwaighofer2013-07-125-9/+69
| | | | | | | | | | | Address calculation for gather/scather in vectorized code can incur a significant cost making vectorization unbeneficial. Add infrastructure to add cost. Tests and cost model for targets will be in follow-up commits. radar://14351991 llvm-svn: 186187
* Relax the test a bit more to handle different UIDs and GIDs.Rafael Espindola2013-07-121-1/+1
| | | | llvm-svn: 186186
* Relax test a bit to handle umask differences.Rafael Espindola2013-07-121-1/+1
| | | | llvm-svn: 186184
* Add a test for the 'o' option in llvm-ar.Rafael Espindola2013-07-121-0/+10
| | | | llvm-svn: 186183
* R600/SI: Add support for f64 kernel argumentsTom Stellard2013-07-122-1/+10
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186182
* R600/SI: Implement select and compares for SITom Stellard2013-07-122-6/+97
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186181
* R600/SI: Add fsqrt pattern for SITom Stellard2013-07-122-2/+30
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186180
* R600/SI: Add double precision fsub pattern for SITom Stellard2013-07-123-3/+42
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186179
* R600/SI: SI support for 64bit ConstantFPTom Stellard2013-07-123-0/+31
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186178
* R600/SI: Add initial double precision support for SITom Stellard2013-07-127-1/+96
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186177
* R600: Add ISA documents to the CompilerWriterInfo pageTom Stellard2013-07-121-0/+11
| | | | llvm-svn: 186176
* Fixed comment in header of Block Frequency Impl and added text for C++ mode.Michael Gottesman2013-07-121-1/+1
| | | | | | | This is a generic block implementation that works on more than machine blocks. The C++ mode addition is a bonus due to the extra space provided. llvm-svn: 186175
* X86: Shrink certain forms of movsx.Benjamin Kramer2013-07-125-6/+62
| | | | | | | | | | | | In particular: movsbw %al, %ax --> cbtw movswl %ax, %eax --> cwtl movslq %eax, %rax --> cltq According to Intel's manual those have the same performance characteristics but come with a smaller encoding. llvm-svn: 186174
* Add static.Rafael Espindola2013-07-121-33/+25
| | | | llvm-svn: 186170
* X86: fold SSE2/AVX2 logical shift by immediate amount into zero vector when ↵Stephen Lin2013-07-123-0/+532
| | | | | | | | possible Patch by Andrea Di Biagio llvm-svn: 186165
* Start using CHECK-LABEL in some tests.Stephen Lin2013-07-1212-110/+111
| | | | llvm-svn: 186163
* Add new directive called CHECK-LABEL to FileCheck.Stephen Lin2013-07-123-29/+194
| | | | | | | | CHECK-LABEL is meant to be used in place on CHECK on lines containing identifiers or other unique labels (they need not actually be labels in the source or output language, though.) This is used to break up the input stream into separate blocks delineated by CHECK-LABEL lines, each of which is checked independently. This greatly improves the accuracy of errors and fix-it hints in many cases, and allows for FileCheck to recover from errors in one block by continuing to subsequent blocks. Some tests will be converted to use this new directive in forthcoming patches. llvm-svn: 186162
* Don't reject an empty archive.Rafael Espindola2013-07-123-4/+10
| | | | llvm-svn: 186159
* Mark MDNode::getOperand as readonly.Benjamin Kramer2013-07-121-1/+1
| | | | | | We can't inline it but we can still CSE calls to it. llvm-svn: 186156
* Revert "indvars: Improve LFTR by eliminating truncation when comparingChandler Carruth2013-07-122-48/+4
| | | | | | | | | | | | | | | | | | | against a constant." This reverts commit r186107. It didn't handle wrapping arithmetic in the loop correctly and thus caused the following C program to count from 0 to UINT64_MAX instead of from 0 to 255 as intended: #include <stdio.h> int main() { unsigned char first = 0, last = 255; do { printf("%d\n", first); } while (first++ != last); } Full test case and instructions to reproduce with just the -indvars pass sent to the original review thread rather than to r186107's commit. llvm-svn: 186152
* Add support for Mips break and syscall insructions. The corresponding test ↵Vladimir Medic2013-07-123-0/+59
| | | | | | cases are added. llvm-svn: 186151
* [SystemZ] Add test missing from r186148Richard Sandiford2013-07-121-0/+82
| | | | | | Sigh, twice in two days sorry. One day I'll remember... llvm-svn: 186150
* [SystemZ] Optimize sign-extends of vector setccsRichard Sandiford2013-07-122-0/+79
| | | | | | | | | | | | | Normal (sext (setcc ...)) sequences are optimised into (select_cc ..., -1, 0) by DAGCombiner::visitSIGN_EXTEND. However, this is deliberately not done for vectors, and after vector type legalization we have (sext_inreg (setcc ...)) instead. I wondered about trying to extend DAGCombiner to handle this case too, but it seemed to be a loss on some other targets I tried, even those for which SETCC isn't "legal" and SELECT_CC is. llvm-svn: 186149
* [SystemZ] Fix parsing of inline asm registersRichard Sandiford2013-07-124-8/+49
| | | | | | | | | | | | GPR and FPR constraints like "{r2}" and "{f2}" weren't handled correctly because the name-to-regno mapping depends on the value type and (because of that) the internal names in RegStrings are not the same as the AsmName. CC constraints like "{cc}" didn't work either because there was no associated register class. llvm-svn: 186148
* [SystemZ] Improve spilling of LGDR and LDGRRichard Sandiford2013-07-122-1/+311
| | | | | | | If the source of these instructions is spilled we should load the destination. If the destination is spilled we should store the source. llvm-svn: 186147
* Stylistic change.Shuxin Yang2013-07-122-3/+3
| | | | | | Thank Nick for figuring out these problems. llvm-svn: 186146
* SLPVectorizer: Sink and enable CSE for ExtractElements.Nadav Rotem2013-07-124-15/+29
| | | | llvm-svn: 186145
* Target/X86: Add explicit Win64 and System V/x86-64 calling conventions.Charles Davis2013-07-1212-33/+110
| | | | | | | | | | | | | | | Summary: This patch adds explicit calling convention types for the Win64 and System V/x86-64 ABIs. This allows code to override the default, and use the Win64 convention on a target that wants to use SysV (and vice-versa). This is needed to implement the `ms_abi` and `sysv_abi` GNU attributes. Reviewers: CC: llvm-svn: 186144
* llvm/test/Object/archive-toc.test: Use env(1) to satisfy win32 hosts.NAKAMURA Takumi2013-07-121-8/+4
| | | | llvm-svn: 186143
* Windows/TimeValue.inc: Mute prefixed '0' on %d to emulate %e.NAKAMURA Takumi2013-07-121-0/+5
| | | | | | It fixes compatibility in llvm/test/Object/archive-toc.test. llvm-svn: 186142
* PEI: refactor replaceFrameIndices(MF) to call replaceFrameIndices(BB).Manman Ren2013-07-122-81/+87
| | | | | | | replaceFrameIndices(MF) will iterate over the BBs and call replaceFrameIndices(BB). No functionality change. llvm-svn: 186141
* SLPVectorize: Replace the code that checks for vectorization candidates in ↵Nadav Rotem2013-07-122-25/+96
| | | | | | | | successor blocks with code that scans PHINodes. Before we could vectorize PHINodes scanning successors was a good way of finding candidates. Now we can vectorize the phinodes which is simpler. llvm-svn: 186139
* Add the ability to use guarded malloc when running llvm lit tests.David Dean2013-07-111-0/+20
| | | | llvm-svn: 186134
* llvm-ar: Clean up memory management with OwningPtr.Benjamin Kramer2013-07-111-15/+9
| | | | llvm-svn: 186131
* Sync SmallBitVector with BitVector. Add unit tests for the missing methods.Benjamin Kramer2013-07-112-0/+70
| | | | llvm-svn: 186123
* Fixed up comments in TargetLowering.h to conform to the LLVM Style Guide.Michael Gottesman2013-07-111-682/+613
| | | | llvm-svn: 186121
* In response to dblaikie's comment on r186035, replacing theAdrian Prantl2013-07-111-136/+163
| | | | | | | | (reduced LLVM IR) + (full source in comment) with the (full LLVM IR) + (reduced src in comment) llvm-svn: 186119
* Add tests for the before and after modifiers.Rafael Espindola2013-07-111-0/+20
| | | | llvm-svn: 186118
* Remove an argument that we dont use anymore.Nadav Rotem2013-07-111-15/+12
| | | | llvm-svn: 186116
* Use %llu to print a 64 bit number. Should fix the ARM bots.Rafael Espindola2013-07-111-1/+1
| | | | llvm-svn: 186113
* Add a test for llvm-ar's m operation.Rafael Espindola2013-07-111-0/+30
| | | | llvm-svn: 186110
* PPC: Add some missing V_SET0 patternsHal Finkel2013-07-112-2/+33
| | | | | | | | | | We had patterns to match v4i32 immAllZerosV -> V_SET0, but not patterns for v8i16 (which occurs in the test case) or v16i8. The same was true for V_SETALLONES (so I added the associated patterns for those as well). Another bug found by llvm-stress. llvm-svn: 186108
* indvars: Improve LFTR by eliminating truncation when comparing against a ↵Andrew Trick2013-07-112-4/+48
| | | | | | | | | | | | | | | | | constant. Patch by Michele Scandale! Adds a special handling of the case where, during the loop exit condition rewriting, the exit value is a constant of bitwidth lower than the type of the induction variable: instead of introducing a trunc operation in order to match correctly the operand types, it allows to convert the constant value to an equivalent constant, depending on the initial value of the induction variable and the trip count, in order have an equivalent comparison between the induction variable and the new constant. llvm-svn: 186107
* PPCDAGToDAGISel::isRunOfOnes should return false on zeroHal Finkel2013-07-112-1/+31
| | | | | | | | | | | | This fixes a bug (found by csmith) at -O0 where we attempt to create a RLWIMI with an out-of-range operand. Most uses of the isRunOfOnes function are guarded by a condition that the value is not zero. This was not true in two places, and in both places a zero input would result in an out-of-rage MB value (= 32). To fix this, isRunOfOnes returns false on a zero input (and I've remove one now-redundant guard). llvm-svn: 186101
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-1111-26/+26
| | | | | | size. llvm-svn: 186098
* Add back code for supporting old mingw versions. Should bring the bots back.Rafael Espindola2013-07-111-3/+13
| | | | llvm-svn: 186096
* Don't use a potentially expensive shift if all we want is one set bit.Benjamin Kramer2013-07-114-6/+6
| | | | | | No functionality change. llvm-svn: 186095
* InsertBefore is the same as AddBefore. Delete it.Rafael Espindola2013-07-111-5/+4
| | | | llvm-svn: 186094
* Looks like some versions of mingw don't have errno_t. Use int.Rafael Espindola2013-07-111-1/+1
| | | | llvm-svn: 186092
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