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* Revert "[DAGCombine] A shuffle of a splat is always the splat itself"Zvi Rackover2017-04-032-12/+10
| | | | | | | | | | This reverts commit r299047 which is incorrect because the simplification may result in incorrect propogation of undefs to users of the folded shuffle. Thanks to Andrea Di Biagio for pointing this out. llvm-svn: 299368
* [Hexagon] Factor out some common code in HexagonEarlyIfConv.cpp, NFCKrzysztof Parzyszek2017-04-031-12/+10
| | | | llvm-svn: 299367
* Revert r299337 "[InstCombine] Remove redundant combine from visitAnd"Craig Topper2017-04-032-0/+89
| | | | | | | | One of the tsan bots started failing at this commit. I don't see anything obviously wrong with the commit so trying this to see if it recovers. Failing log: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-autoconf/builds/6792 llvm-svn: 299366
* [InstCombine] fix formatting for foldLogOpOfMaskedICmps and related bits; NFCISanjay Patel2017-04-031-145/+158
| | | | | | | | | | | | 1. Improve enum, function, and variable names. 2. Improve comments. 3. Fix variable capitalization. 4. Run clang-format. As an existing code comment suggests, this should work with vector types / splat constants too, so making this look right first will reduce the diffs needed for that change. llvm-svn: 299365
* [APInt] Move isMask and isShiftedMask out of APIntOps and into the APInt ↵Craig Topper2017-04-038-43/+54
| | | | | | | | | | class. Implement them without memory allocation for multiword This moves the isMask and isShiftedMask functions to be class methods. They now use the MathExtras.h function for single word size and leading/trailing zeros/ones or countPopulation for the multiword size. The previous implementation made multiple temorary memory allocations to do the bitwise arithmetic operations to match the MathExtras.h implementation. Differential Revision: https://reviews.llvm.org/D31565 llvm-svn: 299362
* [DAGCombiner] Check limits before accessing array element (PR32502)Simon Pilgrim2017-04-031-1/+1
| | | | llvm-svn: 299361
* ARMAsmParser: clean up of isImmediate functionsSjoerd Meijer2017-04-0314-282/+193
| | | | | | | | | | | | | | | | | - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
* [InstCombine] Make foldOpWithConstantIntoOperand take a BinaryOperator ↵Craig Topper2017-04-032-2/+2
| | | | | | | | instead of a generic Instruction. It blindly assumes there are two operands so make it explicit. llvm-svn: 299351
* [InstCombine] Remove a And transform that should be handled by ↵Craig Topper2017-04-031-7/+0
| | | | | | SimplifyDemandedInstructionBits. NFCI llvm-svn: 299349
* Trailing whitespace.NAKAMURA Takumi2017-04-027-8/+8
| | | | llvm-svn: 299344
* Reformat.NAKAMURA Takumi2017-04-022-6/+6
| | | | llvm-svn: 299343
* [APInt] Make use of whichWord and maskBit to simplify some code. NFCCraig Topper2017-04-021-5/+3
| | | | llvm-svn: 299342
* [APInt] Add a public typedef for the internal type of APInt use it instead ↵Craig Topper2017-04-025-167/+169
| | | | | | | | | | | | | | | | of integerPart. Make APINT_BITS_PER_WORD and APINT_WORD_SIZE public. This patch is one step to attempt to unify the main APInt interface and the tc functions used by APFloat. This patch adds a WordType to APInt and uses that in all the tc functions. I've added temporary typedefs to APFloat to alias it to integerPart to keep the patch size down. I'll work on removing that in a future patch. In future patches I hope to reuse the tc functions to implement some of the main APInt functionality. I may remove APINT_ from BITS_PER_WORD and WORD_SIZE constants so that we don't have the repetitive APInt::APINT_ externally. Differential Revision: https://reviews.llvm.org/D31523 llvm-svn: 299341
* [InstCombine] Make InstCombiner::OptAndOp take a BinaryOperator instead of ↵Craig Topper2017-04-022-4/+4
| | | | | | | | | | an Instruction. The callers have already performed the necessary cast before calling. This allows us to remove a comment that says the instruction must be a BinaryOperator and make it explicit in the argument type. Had to add a default case to the switch because BinaryOperator::getOpcode() returns a BinaryOps enum. llvm-svn: 299339
* [X86][MMX] Improve support for folding fptosi from XMM to MMXSimon Pilgrim2017-04-022-7/+13
| | | | llvm-svn: 299338
* [InstCombine] Remove redundant combine from visitAndCraig Topper2017-04-022-89/+0
| | | | | | | | | | As far as I can tell this combine is fully handled by SimplifyDemandedInstructionBits. I was only looking at this because it is the only user of APIntOps::isShiftedMask which is itself broken. As demonstrated by r299187. I was going to fix isShiftedMask and needed to make sure we had coverage for the new cases it would expose to this combine. But looks like we can nuke it instead. Differential Revision: https://reviews.llvm.org/D31543 llvm-svn: 299337
* [X86][MMX] Simplify tablegen patterns by always combining MOVDQ2Q from v2i64Simon Pilgrim2017-04-022-5/+4
| | | | llvm-svn: 299336
* [X86][MMX] Added support for subvector extraction to MMX registerSimon Pilgrim2017-04-022-7/+7
| | | | llvm-svn: 299335
* APInt.h: Prune \param(s) in \returns. [-Wdocumentation]NAKAMURA Takumi2017-04-021-1/+1
| | | | llvm-svn: 299334
* Regenerate test with codegen. NFCI.Simon Pilgrim2017-04-021-4/+10
| | | | llvm-svn: 299333
* Regenerate test with codegen. NFCI.Simon Pilgrim2017-04-021-4/+89
| | | | llvm-svn: 299332
* Regenerate test. NFCI.Simon Pilgrim2017-04-021-56/+56
| | | | llvm-svn: 299331
* NewGVN: Handle coercion of constant stores, loads, memory insts.Daniel Berlin2017-04-026-6/+152
| | | | | | | | | | | | | | | | | Summary: Depends on D30928. This adds support for coercion of stores and memory instructions that do not require insertion to process. Another few tests down. I added the relevant tests from rle.ll Reviewers: davide Subscribers: llvm-commits, Prazek Differential Revision: https://reviews.llvm.org/D30929 llvm-svn: 299330
* [BypassSlowDivision] Do not bypass division of hash-like valuesNikolai Bozhenov2017-04-022-12/+202
| | | | | | | | | | | | | | | | | Disable bypassing if one of the operands looks like a hash value. Slow division often occurs in hashtable implementations and fast division is never taken there because a hash value is extremely unlikely to have enough upper bits set to zero. A value is considered to be hash-like if it is produced by 1) XOR operation 2) Multiplication by a constant wider than the shorter type 3) PHI node with all incoming values being hash-like Differential Revision: https://reviews.llvm.org/D28200 llvm-svn: 299329
* [X86][MMX] Add generic fptosi 4f32-4i32 testSimon Pilgrim2017-04-021-0/+39
| | | | llvm-svn: 299328
* Add another interesting shufflevector test case for InstSimplify. NFC.Zvi Rackover2017-04-021-0/+9
| | | | | | | Test case shows opportunity to constant fold a shuffle with one variable input vector operand. llvm-svn: 299327
* [X86] Use tcAdd/tcSubtract to implement the slow case of operator+=/operator-=.Craig Topper2017-04-021-33/+3
| | | | llvm-svn: 299326
* [APInt] Combine declaration and initialization. NFCCraig Topper2017-04-021-6/+2
| | | | llvm-svn: 299325
* [APInt] Simplify some code by using operator+=(uint64_t) instead of doing a ↵Craig Topper2017-04-021-7/+2
| | | | | | more complex assignment into a temporary APInt just to use the APInt operator+=. llvm-svn: 299324
* [APInt] Fix typo in comment. NFCCraig Topper2017-04-021-1/+1
| | | | llvm-svn: 299323
* MemorySSA: Add support for caching clobbering access in storesDaniel Berlin2017-04-023-24/+55
| | | | | | | | | | | | | | | | Summary: This enables us to cache the clobbering access for stores, despite the fact that we can't rewrite the use-def chains themselves. Early testing shows that, after this change, for larger testcases, it will be a significant net positive (memory and time) to remove the walker caching. Reviewers: george.burgess.iv, davide Subscribers: Prazek, llvm-commits Differential Revision: https://reviews.llvm.org/D31567 llvm-svn: 299322
* [APInt] Use conditional operator to simplify some code. NFCCraig Topper2017-04-011-4/+1
| | | | llvm-svn: 299320
* [APInt] Implement flipAllBitsSlowCase with tcComplement. NFCICraig Topper2017-04-011-2/+1
| | | | llvm-svn: 299319
* [APInt] Fix indentation. NFCCraig Topper2017-04-011-8/+8
| | | | llvm-svn: 299318
* [APInt] Implement AndAssignSlowCase using tcAnd. Do the same for Or and Xor. ↵Craig Topper2017-04-011-9/+3
| | | | | | NFCI llvm-svn: 299317
* [APInt] Allow GreatestCommonDivisor to take rvalue inputs efficiently. Use ↵Craig Topper2017-04-012-8/+6
| | | | | | | | | | | | | | | | | | | moves instead of copies in the loop. Summary: GreatestComonDivisor currently makes a copy of both its inputs. Then in the loop we do one move and two copies, plus any allocation the urem call does. This patch changes it to take its inputs by value so that we can do a move of any rvalue inputs instead of copying. Then in the loop we do 3 move assignments and no copies. This way the only possible allocations we have in the loop is from the urem call. Reviewers: dblaikie, RKSimon, hans Reviewed By: dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31572 llvm-svn: 299314
* [WASM] Remove other comparison of unsigned expression >= 0.Davide Italiano2017-04-011-3/+3
| | | | | | This should finally fix the GCC 7 build with -Werror. llvm-svn: 299313
* [WASM] Remove a set but never used variable.Davide Italiano2017-04-011-4/+1
| | | | llvm-svn: 299312
* [WASM] Remove an assertion that can never fire.Davide Italiano2017-04-011-2/+2
| | | | | | uint* is by definition always >=0. llvm-svn: 299311
* [AMDGPU] Garbage collect now unused dead code. NFCI.Davide Italiano2017-04-011-10/+0
| | | | llvm-svn: 299310
* [InstSimplify] add constant folding for fdiv/fremSanjay Patel2017-04-012-74/+51
| | | | | | Also, add a helper function so we don't have to repeat this code for each binop. llvm-svn: 299309
* [InstSimplify] add tests for missed constant folding; NFCSanjay Patel2017-04-011-3/+21
| | | | llvm-svn: 299308
* fix formatting; NFCSanjay Patel2017-04-011-34/+35
| | | | llvm-svn: 299307
* fix formatting; NFCSanjay Patel2017-04-012-104/+94
| | | | llvm-svn: 299305
* [DAGCombiner] enable vector transforms for any/all {sign} bits set/clearSanjay Patel2017-04-013-72/+54
| | | | | | | | The code already allowed vector types in via "isInteger" (which might want a more specific name), so use splat-friendly constant predicates to match those types. llvm-svn: 299304
* [PowerPC, x86] add vector tests for any/all {sign} bits set/clear; NFCSanjay Patel2017-04-012-0/+237
| | | | llvm-svn: 299303
* MemorySSA: Update expensive checking version of def_chain_iterator for ↵Daniel Berlin2017-04-011-1/+1
| | | | | | templating changes llvm-svn: 299301
* NewGVN: Don't try to kill off the stored value of stores whenDaniel Berlin2017-04-011-9/+22
| | | | | | | | | | | | | processing the congruence class of the store. Because we use the stored value of a store as the def, it isn't dead just because it appears as a def when it comes from a store. Note: I have not hit any cases with the memory code as it is where this breaks anything, just because of what memory congruences we actually allow. In a followup that improves memory congruence, this bug actually breaks real stuff (but the verifier catches it). llvm-svn: 299300
* NewGVN: Clean up GVNExpression memory hierarchy, restructure hash ↵Daniel Berlin2017-04-012-75/+75
| | | | | | computation a bit so we don't have to redefine it for loads, stores, and calls llvm-svn: 299299
* NewGVN: Use def_chain iterator in singleReachablePhiPath instead of recursionDaniel Berlin2017-04-012-28/+34
| | | | llvm-svn: 299298
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