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* [LV] Update type in cost model for scalarizationMatthew Simpson2017-05-242-6/+41
| | | | | | | | | | | | | | For non-uniform instructions marked for scalarization, we should update `VectorTy` when computing instruction costs to reflect the scalar type. In addition to determining instruction costs, this type is also used to signal that all instructions in the loop will be scalarized. This currently affects memory instructions and non-pointer induction variables and their updates. (We also mark GEPs scalar after vectorization, but their cost is computed together with memory instructions.) For scalarized induction updates, this patch also scales the scalar cost by the vectorization factor, corresponding to each induction step. llvm-svn: 303763
* [MSP430] Fix PR33050: Don't use ADD16ri to lower FrameIndex.Vadzim Dambrouski2017-05-244-4/+9
| | | | | | | | | Use ADDframe pseudo instruction instead. This will fix machine verifier error, and will help to fix PR32146. Differential Revision: https://reviews.llvm.org/D33452 llvm-svn: 303758
* [InstCombine] add tests to show potential missing folds; NFCSanjay Patel2017-05-241-0/+39
| | | | | | | | | As noted in https://bugs.llvm.org/show_bug.cgi?id=33138 and the comments, there are multiple ways to view this. If we choose not to solve this in InstCombine, these tests will serve as documentation of that choice. llvm-svn: 303755
* Revert "AMDGPU: Fold CI-specific complex SMRD patterns into existing complex ↵Marek Olsak2017-05-244-18/+51
| | | | | | | | | | | patterns" This reverts commit e065977c4b5f68ab845400b256f6a3822b1325fa. It doesn't work. S_LOAD_DWORD_IMM_ci and friends aren't selected by any of the patterns, so it was putting 32-bit literals into the 8-bit field. llvm-svn: 303754
* [InstCombine] add tests to document bitcast + bitwise-logic behavior; NFCSanjay Patel2017-05-241-0/+45
| | | | | | | | The solution for PR26702 ( https://bugs.llvm.org/show_bug.cgi?id=26702 ) added a canonicalization rule, but the minimal regression tests don't demonstrate how that rule interacts with other folds. llvm-svn: 303750
* Revert "[SCEV] Do not fold dominated SCEVUnknown into AddRecExpr start"Diana Picus2017-05-247-180/+20
| | | | | | This reverts commit r303730 because it broke all the buildbots. llvm-svn: 303747
* [Hexagon] Fix comment in HexagonPacketizer::runOnMachineFunctionKrzysztof Parzyszek2017-05-241-2/+2
| | | | | | | | Patch by Wei-Ren Chen. Differential Revision: https://reviews.llvm.org/D33439 llvm-svn: 303745
* [LoopVectorizer] Let target prefer scalar addressing computations.Jonas Paulsson2017-05-246-0/+160
| | | | | | | | | | | | | | | | | | | | | | The loop vectorizer usually vectorizes any instruction it can and then extracts the elements for a scalarized use. On SystemZ, all elements containing addresses must be extracted into address registers (GRs). Since this extraction is not free, it is better to have the address in a suitable register to begin with. By forcing address arithmetic instructions and loads of addresses to be scalar after vectorization, two benefits result: * No need to extract the register * LSR optimizations trigger (LSR isn't handling vector addresses currently) Benchmarking show improvements on SystemZ with this new behaviour. Any other target could try this by returning false in the new hook prefersVectorizedAddressing(). Review: Renato Golin, Elena Demikhovsky, Ulrich Weigand https://reviews.llvm.org/D32422 llvm-svn: 303744
* [SystemZ] Fix register modelling in expandLoadStackGuard()Jonas Paulsson2017-05-241-16/+14
| | | | | | | | EXPENSIVE_CHECKS found this bug (https://bugs.llvm.org/show_bug.cgi?id=33047), which this patch fixes. The EAR instruction defines a GR32, not a GR64. Review: Ulrich Weigand llvm-svn: 303743
* Demangler: Fix constructor cv qualifier handlingTamas Berghammer2017-05-241-0/+2
| | | | | | | | | | | | | Previously if we parsed a constructor then we set parsed_ctor_dtor_cv to true and never reseted it. This causes issue when a template argument references a constructor (e.g. type of lambda defined inside a constructor) as we will have the parsed_ctor_dtor_cv flag set what will cause issues when parsing later arguments. Differential Revision: https://reviews.llvm.org/D33385 libcxxabi change: https://reviews.llvm.org/rL303737 llvm-svn: 303738
* Strip trailing whitespace. NFCI.Simon Pilgrim2017-05-241-2/+2
| | | | llvm-svn: 303736
* [ARM] Remove ThumbTargetMachines. (NFC)Florian Hahn2017-05-243-114/+15
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Thumb code generation is controlled by ARMSubtarget and the concrete ThumbLETargetMachine and ThumbBETargetMachine are not needed. Eric Christopher suggested removing the unneeded target machines in https://reviews.llvm.org/D33287. I think it still makes sense to keep separate TargetMachines for big and little endian as we probably do not want to have different endianess for difference functions in a single compilation unit. The MIPS backend has two separate TargetMachines for big and little endian as well. Reviewers: echristo, rengolin, kristof.beyls, t.p.northover Reviewed By: echristo Subscribers: aemerson, javed.absar, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D33318 llvm-svn: 303733
* MachineCSE: Respect interblock physreg livenessMikael Holmen2017-05-242-2/+37
| | | | | | | | | | | | | | | | | | | | Summary: This is a fix for PR32538. MachineCSE first looks at MO.isDead(), but if it is not marked dead, MachineCSE still wants to do its own check to see if it is trivially dead. This check for the trivial case assumed that physical registers cannot be live out of a block. Patch by Mattias Eriksson. Reviewers: qcolombet, jbhateja Reviewed By: qcolombet, jbhateja Subscribers: jbhateja, llvm-commits Differential Revision: https://reviews.llvm.org/D33408 llvm-svn: 303731
* [SCEV] Do not fold dominated SCEVUnknown into AddRecExpr startMax Kazantsev2017-05-247-20/+180
| | | | | | | | | | | | | | | | | | | | | | | | | | | When folding arguments of AddExpr or MulExpr with recurrences, we rely on the fact that the loop of our base recurrency is the bottom-lost in terms of domination. This assumption may be broken by an expression which is treated as invariant, and which depends on a complex Phi for which SCEVUnknown was created. If such Phi is a loop Phi, and this loop is lower than the chosen AddRecExpr's loop, it is invalid to fold our expression with the recurrence. Another reason why it might be invalid to fold SCEVUnknown into Phi start value is that unlike other SCEVs, SCEVUnknown are sometimes position-bound. For example, here: for (...) { // loop phi = {A,+,B} } X = load ... Folding phi + X into {A+X,+,B}<loop> actually makes no sense, because X does not exist and cannot exist while we are iterating in loop (this memory can be even not allocated and not filled by this moment). It is only valid to make such folding if X is defined before the loop. In this case the recurrence {A+X,+,B}<loop> may be existant. This patch prohibits folding of SCEVUnknown (and those who use them) into the start value of an AddRecExpr, if this instruction is dominated by the loop. Merging the dominating unknown values is still valid. Some tests that relied on the fact that some SCEVUnknown should be folded into AddRec's are changed so that they no longer expect such behavior. llvm-svn: 303730
* Explicitly set CPU and -slow-incdec to try to fix r303678's test on ↵Daniel Sanders2017-05-241-1/+1
| | | | | | llvm-clang-x86_64-expensive-checks-win. llvm-svn: 303727
* [APInt] Use std::end to avoid mentioning the size of a local buffer repeatedly.Craig Topper2017-05-241-2/+2
| | | | llvm-svn: 303726
* Revert r303720: Tweak r303678's test to try to fix ↵Daniel Sanders2017-05-241-1/+1
| | | | | | | | llvm-clang-x86_64-expensive-checks-win. It doesn't fix that builder. llvm-svn: 303721
* Tweak r303678's test to try to fix llvm-clang-x86_64-expensive-checks-win.Daniel Sanders2017-05-241-1/+1
| | | | | | | | I suspect this buildbot has slow-incdec set by default, most likely due to the default CPU having this set. This feature bit can prevent optsize from having an effect on this IR. llvm-svn: 303720
* [ARM] Add VLDx/VSTx sched defs for machine-schedulers. NFCIJaved Absar2017-05-245-337/+292
| | | | | | | | | | This patch adds missing scheds for Neon VLDx/VSTx instructions. This will help one write schedulers easier/faster in the future for ARM sub-targets. Existing models will not affected by this patch. Reviewed by: Renato Golin, Diana Picus Differential Revision: https://reviews.llvm.org/D33120 llvm-svn: 303717
* [NewGVN] Update additionalUsers when we simplify to a value.Davide Italiano2017-05-242-0/+49
| | | | | | | | | | Otherwise we don't revisit an instruction that could be simplified, and when we verify, we discover there's something that changed, i.e. what we had wasn't a maximal fixpoint. Fixes PR32836. llvm-svn: 303715
* Fix broken build.Zachary Turner2017-05-242-4/+3
| | | | llvm-svn: 303711
* Revert "Disable coverage opt-out for strong postdominator blocks."George Karpenkov2017-05-242-29/+22
| | | | | | | This reverts commit 2ed06f05fc10869dd1239cff96fcdea2ee8bf4ef. Buildbots do not like this on Linux. llvm-svn: 303710
* Revert "Fixes for tests for r303698"George Karpenkov2017-05-242-7/+2
| | | | | | This reverts commit 69bfaf72e7502eb08bbca88a57925fa31c6295c6. llvm-svn: 303709
* git-llvm script should add .exe on Windows.Zachary Turner2017-05-241-0/+2
| | | | llvm-svn: 303708
* Don't do a full scan of the type stream before processing records.Zachary Turner2017-05-242-14/+14
| | | | | | | | | | | | | LazyRandomTypeCollection is designed for random access, and in order to provide this it lazily indexes ranges of types. In the case of types from an object file, there is no partial index to build off of, so it has to index the full stream up front. However, merging types only requires sequential access, and when that is needed, this extra work is simply wasted. Changing the algorithm to work on sequential arrays of types rather than random access type collections eliminates this up front scan. llvm-svn: 303707
* [SCCP] Use the `hasAddressTaken()` version defined in `Function`.Davide Italiano2017-05-231-1/+2
| | | | | | | | | | Instead of using the SCCP homegrown one. We should eventually make the private SCCP version disappear, but that wont' be today. PR33143 tracks this issue. Add braces for consistency while here. No functional change intended. llvm-svn: 303706
* [LIR] Use the newly `getRecurrenceVar()` helper. NFCI.Davide Italiano2017-05-231-4/+4
| | | | llvm-svn: 303704
* Fixes for tests for r303698George Karpenkov2017-05-232-2/+7
| | | | llvm-svn: 303701
* [LIR] Strengthen the check for recurrence variable in popcnt/CTLZ.Davide Italiano2017-05-232-9/+51
| | | | | | | Fixes PR33114. Differential Revision: https://reviews.llvm.org/D33420 llvm-svn: 303700
* Disable coverage opt-out for strong postdominator blocks.George Karpenkov2017-05-232-22/+29
| | | | | | | | | | | | | | | | Coverage instrumentation has an optimization not to instrument extra blocks, if the pass is already "accounted for" by a successor/predecessor basic block. However (https://github.com/google/sanitizers/issues/783) this reasoning may become circular, which stops valid paths from having coverage. In the worst case this can cause fuzzing to stop working entirely. This change simplifies logic to something which trivially can not have such circular reasoning, as losing valid paths does not seem like a good trade-off for a ~15% decrease in the # of instrumented basic blocks. llvm-svn: 303698
* Revert LLVM changes for "Sema: allow imaginary constants via GNU extension ↵Tim Northover2017-05-231-4/+1
| | | | | | | | if UDL overloads not present." The changes accidentally crept into a Clang commit I was making. llvm-svn: 303697
* [git-llvm] Check if svn is installed.Rui Ueyama2017-05-231-0/+8
| | | | | | | | | | | | | The error message that git-llvm script prints out when svn is missing is very cryptic. I spent a fair amount of time to find what was wrong with my environment. It looks like many newcomers also exprienced a hard time to submit their first patches due to this error. This patch adds a more user-friendly error message. Differential Revision: https://reviews.llvm.org/D33458 llvm-svn: 303696
* [MSP430] Add subtarget features for hardware multiplier.Vadzim Dambrouski2017-05-237-25/+57
| | | | | | | | Also add more processors to make -mcpu option behave similar to gcc. Differential Revision: https://reviews.llvm.org/D33335 llvm-svn: 303695
* Sema: allow imaginary constants via GNU extension if UDL overloads not present.Tim Northover2017-05-231-1/+4
| | | | | | | | | | | | | C++14 added user-defined literal support for complex numbers so that you can write something like "complex<double> val = 2i". However, there is an existing GNU extension supporting this syntax and interpreting the result as a _Complex type. This changes parsing so that such literals are interpreted in terms of C++14's operators if an overload is present but otherwise falls back to the original GNU extension. llvm-svn: 303694
* Silence MSVC warning about unsigned integer overflow, which has defined behaviorReid Kleckner2017-05-231-1/+3
| | | | llvm-svn: 303693
* abtest: remove duplicate scriptFrancis Visoiu Mistrih2017-05-231-234/+0
| | | | | | | | This is fixing a mistake from r303690. Differential Revision: https://reviews.llvm.org/D33303 llvm-svn: 303692
* [AMDGPU] Add INDIRECT_BASE_ADDR to R600_Reg32 class (PR33045)Simon Pilgrim2017-05-2318-24/+24
| | | | | | | | This fixes 17 of the 41 -verify-machineinstrs test failures identified in PR33045 Differential Revision: https://reviews.llvm.org/D33451 llvm-svn: 303691
* AsmPrinter: mark the beginning and the end of a function in verbose modeFrancis Visoiu Mistrih2017-05-239-142/+282
| | | | llvm-svn: 303690
* merge-request.sh: Use https url for bugzillaTom Stellard2017-05-231-1/+1
| | | | | | | | With the http url, the script fails with: Connection lost/failed: 411 Client Error: Length Required llvm-svn: 303685
* AMDGPU/SI: Move the local memory usage related checking after calling ↵Changpeng Fang2017-05-232-99/+136
| | | | | | | | | | | | | | | | | convention checking in PromoteAlloca Summary: Promoting Alloca to Vector and Promoting Alloca to LDS are two independent handling of Alloca and should not affect each other. As a result, we should not give up promoting to vector if there is not enough LDS. This patch factors out the local memory usage related checking out and replace it after the calling convention checking. Reviewer: arsenm Differential Revision: http://reviews.llvm.org/D33139 llvm-svn: 303684
* Fix unused variable warnings after r303678Daniel Sanders2017-05-231-2/+2
| | | | | | This should fix lld-x86_64-darwin13 llvm-svn: 303683
* [AArch64][Falkor] Refine sched details for LSLfast/ASRfast.Geoff Berry2017-05-234-40/+189
| | | | llvm-svn: 303682
* [AMDGPU] Combine and (srl) into shl (bfe)Stanislav Mekhanoshin2017-05-234-11/+81
| | | | | | | | | | | | | | | | | | | Perform DAG combine: and (srl x, c), mask => shl (bfe x, nb + c, mask >> nb), nb Where nb is a number of trailing zeroes in mask. It replaces two instructions with two and BFE is generally a more expensive one. However this is only done if we are selecting a byte or word at an aligned boundary which results in a proper SDWA operand pattern. It is only done if SDWA is supported. TODO: improve SDWA pass to actually convert this pattern. It is not done now because we have an immediate in the instruction, which has be moved into a VGPR. Differential Revision: https://reviews.llvm.org/D33455 llvm-svn: 303681
* [AArch64][Falkor] Fix sched details for FMOV of WZR/XZR.Geoff Berry2017-05-232-6/+8
| | | | llvm-svn: 303680
* [ARM] Temporarily disable globals promotion to constant pools to prevent ↵Oleg Ranevskyy2017-05-234-16/+16
| | | | | | | | | | | | | | | | | | | | | miscompilation Summary: A temporary workaround for PR32780 - rematerialized instructions accessing the same promoted global through different constant pool entries. The patch turns off the globals promotion optimization leaving all its code in place, so that it can be easily turned on once PR32780 is fixed. Since this is a miscompilation issue causing generation of misbehaving code, and the problem is very subtle, the patch might be valuable enough to get into 4.0.1. Reviewers: efriedma, jmolloy Reviewed By: efriedma Subscribers: aemerson, javed.absar, llvm-commits, rengolin, asl, tstellar Differential Revision: https://reviews.llvm.org/D33446 llvm-svn: 303679
* [globalisel][tablegen] Add support for (set $dst, 1) and test X86's ↵Daniel Sanders2017-05-233-18/+187
| | | | | | | | | | | | | | | | | | | | | | | | | OptForSize predicate. Summary: It's rare but a small number of patterns use IntInit's at the root of the match. On X86, one such rule is enabled by the OptForSize predicate and causes the compiler to use the smaller: %0 = MOV32r1 instead of the usual: %0 = MOV32ri 1 This patch adds support for matching IntInit's at the root and uses this as a test case for the optsize attribute that was implemented in r301750 Reviewers: qcolombet, ab, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: qcolombet Subscribers: igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32791 llvm-svn: 303678
* [CodeView] Eliminate redundant hashes and allocations.Zachary Turner2017-05-232-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When writing field list records, we would construct a temporary type serializer that shared a bump ptr allocator with the rest of the application, so anything allocated from here would live forever. Furthermore, this temporary serializer had all the properties of a full blown serializer including record hashing and de-duplication. These features are required when you're merging multiple type streams into each other, because different streams may contain identical records, but records from the same type stream will never collide with each other. So all of this hashing was unnecessary. To solve this, two fixes are made: 1) The temporary serializer keeps its own bump ptr allocator instead of sharing a global one. When it's finished, all of its memory is freed. 2) Instead of using the same temporary serializer for the life of an entire type stream, we use it only for the life of a single field list record and delete it when the field list record is completed. This way the hash table will not grow as other records from the same type stream get inserted. Further improvements could eliminate hashing entirely from this codepath. This reduces the link time by 85% in my test, from 1 minute to 9 seconds. llvm-svn: 303676
* [DAG] Add AddressSpace parameter to canMergeStoresTo. NFC.Nirav Dave2017-05-233-9/+14
| | | | llvm-svn: 303673
* [InstSimplify] Add more tests for undef inputs and multiplying by 0 for the ↵Craig Topper2017-05-231-0/+92
| | | | | | add/sub/mul with overflow intrinsics. NFC llvm-svn: 303671
* [GSoC] Shell autocompletion for clangYuka Takahashi2017-05-232-0/+22
| | | | | | | | | | | | | | | | | Summary: This is a first patch for GSoC project, bash-completion for clang. To use this on bash, please run `source clang/utils/bash-autocomplete.sh`. bash-autocomplete.sh is code for bash-completion. Simple flag completion and path completion is available in this patch. Reviewers: teemperor, v.g.vassilev, ruiu, Bigcheese, efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D33237 llvm-svn: 303670
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