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* [DWARF] NFC: Make string-offset handling more like address-table handling; Paul Robinson2017-06-273-14/+3
| | | | | | do the indirection and relocation all in the same method. llvm-svn: 306418
* [PatternMatch] Remove 64-bit or less restriction from m_SpecificIntCraig Topper2017-06-272-12/+5
| | | | | | | | | | Not sure why this restriction existed, but it seems like we should support any size Constant here. The particular pattern in the tests is not the only use of this matcher in the tree. There's one in CodeGenPrepare and one in InstSimplify as well. Differential Revision: https://reviews.llvm.org/D34666 llvm-svn: 306417
* [JumpThreading] Add test case that was supposed to go with r306085.Craig Topper2017-06-271-0/+125
| | | | | | Looks like I forgot to 'git add' when I submitted the commit. Thanks to Chandler for noticing. llvm-svn: 306416
* Updated and extended the information about each instruction in HSW and SNB ↵Gadi Haber2017-06-2733-5266/+9564
| | | | | | | | | | | | | | | | | | | to include the following data: •static latency •number of uOps from which the instructions consists •all ports used by the instruction Reviewers:  RKSimon zvi aymanmus m_zuckerman Differential Revision: https://reviews.llvm.org/D33897 llvm-svn: 306414
* [AMDGPU] SDWA: several fixes for V_CVT and VOPC instructionsSam Kolton2017-06-278-34/+490
| | | | | | | | | | | | | | Summary: 1. Instruction V_CVT_U32_F32 allow omod operand (see SIInstrInfo.td:1435). In fact this operand shouldn't be allowed here. This fix checks if SDWA pseudo instruction has OMod operand and then copy it. 2. There were several problems with support of VOPC instructions in SDWA peephole pass. Reviewers: tstellar, arsenm, vpykhtin, airlied, kzhuravl Subscribers: wdng, nhaehnle, yaxunl, dstuttard, tpr, sarnex, t-tye Differential Revision: https://reviews.llvm.org/D34626 llvm-svn: 306413
* [AArch64] Update successor probabilities after ccmp-conversionMatthew Simpson2017-06-273-7/+93
| | | | | | | | | | | | | This patch modifies the conditional compares pass so that it keeps successor probabilities up-to-date after the conversion. Previously, successor probabilities were being normalized to a uniform distribution, even though they may have been heavily biased prior to the conversion (e.g., if one of the edges was the back edge of a loop). This loss of information affected passes later in the pipeline. Differential Revision: https://reviews.llvm.org/D34109 llvm-svn: 306412
* [LoopUnrollRuntime] Use SCEV exit count for calculating trip count. NFCIAnna Thomas2017-06-271-1/+5
| | | | | | | Instead of getBackEdgeTakenCount, use getExitCount on the latch exiting block (which is proven to be the only exiting block in the loop to be unrolled). llvm-svn: 306410
* [mips] Add instruction aliases for ds(r|l)l.Simon Dardis2017-06-2711-6/+60
| | | | | | | Add the instruction aliases for ds(r|l)l for the two operand alias of ds(r|l)lv and the aliases ds(r|l)l with the three register operands. llvm-svn: 306405
* [SelectionDAG] set dereferenceable flag in MergeConsecutiveStores to fix ↵Hiroshi Inoue2017-06-272-2/+36
| | | | | | | | | | | | assetion failure When SelectionDAG merges consecutive stores and loads in MergeConsecutiveStores, it does not set dereferenceable flag for a created load instruction. This results in an assertion failure if SelectionDAG commonizes this load instruction with other load instructions, as well as it may miss optimization opportunities. This patch sat dereferenceable flag for the newly created load instruction if all the load instructions to be merged are dereferenceable. Differential Revision: https://reviews.llvm.org/D34679 llvm-svn: 306404
* Recommitting rL305465 after fixing bug in TableGen in rL306251 & rL306371Ayman Musa2017-06-276-357/+14296
| | | | | | | | | | | | | | | [X86][AVX512] Improve lowering of AVX512 compare intrinsics (remove redundant shift left+right instructions). AVX512 compare instructions return v*i1 types. In cases where the number of elements in the returned value are less than 8, clang adds zeroes to get a mask of v8i1 type. Later on it's replaced with CONCAT_VECTORS, which then is lowered to many DAG nodes including insert/extract element and shift right/left nodes. The fact that AVX512 compare instructions put the result in a k register and zeroes all its upper bits allows us to remove the extra nodes simply by copying the result to the required register class. When lowering, identify these cases and transform them into an INSERT_SUBVECTOR node (marked legal), then catch this pattern in instructions selection phase and transform it into one avx512 cmp instruction. Differential Revision: https://reviews.llvm.org/D33188 llvm-svn: 306402
* Add missing include. Should fix modules libstdc++ builds.Vassil Vassilev2017-06-271-0/+1
| | | | llvm-svn: 306399
* fix trivial typos, NFCHiroshi Inoue2017-06-273-6/+6
| | | | | | succesor -> successor llvm-svn: 306393
* [ARM] GlobalISel: Support G_SELECT for pointersDiana Picus2017-06-274-3/+77
| | | | | | All we need to do is mark it as legal, otherwise it's just like s32. llvm-svn: 306390
* [X86][AVX512] Regenerate avx512 arithmetic testsSimon Pilgrim2017-06-271-129/+129
| | | | llvm-svn: 306389
* [globalisel][tablegen] Add support for EXTRACT_SUBREG.Daniel Sanders2017-06-275-14/+245
| | | | | | | | | | | | | | | | Summary: After this patch, we finally have test cases that require multiple instruction emission. Depends on D33590 Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls Subscribers: javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D33596 llvm-svn: 306388
* [mips] Refine the condition for when to use CALL16 vs a GOT displacement.Simon Dardis2017-06-271-2/+6
| | | | | | | | | | | | | | Borrow from the logic for 'jal' in MipsAsmParser::processInstruction and add the extra condition of bypassing CALL16 if the destination symbol is an ELF symbol with STB_LOCAL binding. Patch by: John Baldwin Reviewers: sdardis Differential Revision: https://reviews.llvm.org/D33999 llvm-svn: 306387
* [ARM] GlobalISel: Support G_SELECT for i32Diana Picus2017-06-277-0/+171
| | | | | | | | | | * Mark as legal for (s32, i1, s32, s32) * Map everything into GPRs * Select to two instructions: a CMP of the condition against 0, to set the flags, and a MOVCCr to select between the two inputs based on the flags that we've just set llvm-svn: 306382
* Recommitting 306331.Ayal Zaks2017-06-271-287/+300
| | | | | | | Undoing revert 306338 after fixed bug: add metadata to the load instead of the reverse shuffle added to it, retaining the original ValueMap implementation. llvm-svn: 306381
* [PowerPC] fix incorrect processor name for -mcpu in a test caseHiroshi Inoue2017-06-271-1/+1
| | | | | | to surpress warnings. ppc970 should be 970 (or g5) llvm-svn: 306380
* [SROA] Fix PR32902 by more carefully propagating !nonnull metadata.Chandler Carruth2017-06-272-2/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is based heavily on the work done ni D34285. I mostly wanted to do test cleanup for the author to save them some time, but I had a really hard time understanding why it was so hard to write better test cases for these issues. The problem is that because SROA does a second rewrite of the loads and because we *don't* propagate !nonnull for non-pointer loads, we first introduced invalid !nonnull metadata and then stripped it back off just in time to avoid most ways of this PR manifesting. Moving to the more careful utility only fixes this by changing the predicate to look at the new load's type rather than the target type. However, that *does* fix the bug, and the utility is much nicer including adding range metadata to model the nonnull property after a conversion to an integer. However, we have bigger problems because we don't actually propagate *range* metadata, and the utility to do this extracted from instcombine isn't really in good shape to do this currently. It *only* handles the case of copying range metadata from an integer load to a pointer load. It doesn't even handle the trivial cases of propagating from one integer load to another when they are the same width! This utility will need to be beefed up prior to using in this location to get the metadata to fully survive. And even then, we need to go and teach things to turn the range metadata into an assume the way we do with nonnull so that when we *promote* an integer we don't lose the information. All of this will require a new test case that looks kind-of like `preserve-nonnull.ll` does here but focuses on range metadata. It will also likely require more testing because it needs to correctly handle changes to the integer width, especially as SROA actively tries to change the integer width! Last but not least, I'm a little worried about hooking the range metadata up here because the instcombine logic for converting from a range metadata *to* a nonnull metadata node seems broken in the face of non-zero address spaces where null is not mapped to the integer `0`. So that probably needs to get fixed with test cases both in SROA and in instcombine to cover it. But this *does* extract the core PR fix from D34285 of preventing the !nonnull metadata from being propagated in a broken state just long enough to feed into promotion and crash value tracking. On D34285 there is some discussion of zero-extend handling because it isn't necessary. First, the new load size covers all of the non-undef (ie, possibly initialized) bits. This may even extend past the original alloca if loading those bits could produce valid data. The only way its valid for us to zero-extend an integer load in SROA is if the original code had a zero extend or those bits were undef. And we get to assume things like undef *never* satifies nonnull, so non undef bits can participate here. No need to special case the zero-extend handling, it just falls out correctly. The original credit goes to Ariel Ben-Yehuda! I'm mostly landing this to save a few rounds of trivial edits fixing style issues and test case formulation. Differental Revision: D34285 llvm-svn: 306379
* Add missing forward declaraion.Vassil Vassilev2017-06-271-0/+1
| | | | llvm-svn: 306376
* AMDGPU: M0 operands to spill/restore opcodes are deadNicolai Haehnle2017-06-272-2/+24
| | | | | | | | | | | | | | | | | Summary: With scalar stores, M0 is clobbered and therefore marked as implicitly defined. However, it is also dead. This fixes an assertion when the Greedy Register Allocator decides to optimize a spill/restore pair away again (via tryHintsRecoloring). Reviewers: arsenm Subscribers: qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33319 llvm-svn: 306375
* [TableGen] Fix bug in TableGen CodeGenPatterns when adding variants of the ↵Ayman Musa2017-06-271-2/+2
| | | | | | | | | | | | | | | | | patterns. All patterns reside in a std::vector container, where new variants are added to it using the standard library's emplace_back function. When calling this with a new element while there is no enough allocated space, a bigger space is allocated and all the old info in the small vector is copied to the newly allocated vector, then the old vector is freed. The problem is that before doing this "copying", we take a reference of one of the elements in the old vector, and after the "copying" we add it to the new vector. As the old vector is freed after the copying, the reference now does not point to a valid element. Added new function to the API of CodeGenDAGPatterns class to return the same information as a copy in order to avoid this issue. This was revealed in rL305465 that added many patterns and forced the reallocation of the vector which caused crashes in windows bots. Differential Revision: https://reviews.llvm.org/D34341 llvm-svn: 306371
* [GlobalISel][X86] Add fp32/62 legalizer, regbank-select, selection tests for ↵Igor Breger2017-06-2715-157/+970
| | | | | | G_FADD, G_FSUB, G_FMUL, G_FDIV. NFC. llvm-svn: 306370
* Fixed the warning introduced by r306289 to make ubuntu-gcc7.1-werror bot green.Galina Kistanova2017-06-271-1/+1
| | | | llvm-svn: 306369
* [Reassociate] Make sure EraseInst sets MadeChangeMikael Holmen2017-06-272-0/+31
| | | | | | | | | | | | | | | | | | | | | Summary: EraseInst didn't report that it made IR changes through MadeChange. It is essential that changes to the IR are reported correctly, since for example ReassociatePass::run() will indicate that all analyses are preserved otherwise. And the CGPassManager determines if the CallGraph is up-to-date based on status from InstructionCombiningPass::runOnFunction(). Reviewers: craig.topper, rnk, davide Reviewed By: rnk, davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34616 llvm-svn: 306368
* [PowerPC] set optimization level in SelectionDAGISelHiroshi Inoue2017-06-277-51/+53
| | | | | | | | | PowerPC backend does not pass the current optimization level to SelectionDAGISel and so SelectionDAGISel works with the default optimization level regardless of the current optimization level. This patch makes the PowerPC backend set the optimization level correctly. Differential Revision: https://reviews.llvm.org/D34615 llvm-svn: 306367
* [COFF, ARM64] Fix typo in COFF ARM64 Relocation TypeMandeep Singh Grang2017-06-271-1/+1
| | | | | | | | | | | | | | | | Summary: Fixed IMAGE_REL_ARM64_PAGEBASE_REL2 ==> IMAGE_REL_ARM64_PAGEBASE_REL21 Refer: http://www.microsoft.com/whdc/system/platform/firmware/PECOFF.mspx Reviewers: zturner, rnk, ruiu Reviewed By: ruiu Subscribers: aemerson, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34659 llvm-svn: 306366
* [InstCombine] Add test cases demonstrating that we don't optmize ↵Craig Topper2017-06-271-0/+27
| | | | | | select+cmp+cttz/ctlz when the bitwidth is larger than 64 bits. llvm-svn: 306365
* [AVR] Migrate to new MCAsmBackend applyFixup and processFixupValueLeslie Zhai2017-06-272-28/+26
| | | | | | | | | | | | Reviewers: rafael, dylanmckay, jroelofs, meadori Reviewed By: rafael, meadori Subscribers: meadori, llvm-commits Differential Revision: https://reviews.llvm.org/D34551 llvm-svn: 306359
* [SROA] Further test cleanup and add a test for the actual propagation ofChandler Carruth2017-06-271-4/+25
| | | | | | the nonnull attribute distinct from rewriting it into an assume. llvm-svn: 306358
* [CFLAA] Move FunctionHandle to llvm::cflaa.Davide Italiano2017-06-273-5/+4
| | | | | | | Also, while here, remove an unneeded `using namespace llvm`. Thanks to George for the suggestion. llvm-svn: 306355
* [CFLAA] Move a common function to the header to reduce duplication.Davide Italiano2017-06-273-24/+17
| | | | | | Differential Revision: https://reviews.llvm.org/D34660 llvm-svn: 306354
* [SROA] Clean up a test case a bit prior to adding more testing forChandler Carruth2017-06-271-15/+13
| | | | | | nonnull as part of fixing PR32902. llvm-svn: 306353
* ScheduleDAGInstrs: Fix fixupKills() adding too many kill flags.Matthias Braun2017-06-272-1/+46
| | | | | | | | | Remove invalid shortcut in fixupKills(): A register needs to be marked live even when we are not adding a kill flag. This is because a partially live register must not get a kill flags, but it still needs to be fully marked live when walking backwards. llvm-svn: 306352
* [CFLAA] Use raw pointers instead of Optional<Pointer>. NFC.Davide Italiano2017-06-271-9/+9
| | | | | | | | | Using Optional<> here doesn't seem to be terribly valuable, but this is not the main point of this change. The change enables us to merge the (now) two identical copies of parentFunctionOfValue() that Steensgaard's and Andersens' provide. llvm-svn: 306351
* [CFLAA] Change FunctionHandle to be common to Steensgaard's and Andersens'Davide Italiano2017-06-265-49/+52
| | | | | | Differential Revision: https://reviews.llvm.org/D34638 llvm-svn: 306348
* DAGCombine: Make sure we only eliminate trunc/extend when the scales of ↵Wolfgang Pieb2017-06-262-5/+44
| | | | | | | | | | | | truncation and extension match. This fixes PR33368. Reviewer: rksimon Differential Revision: https://reviews.llvm.org/D34069 llvm-svn: 306345
* revert r306336 for breaking ppc test.Dehao Chen2017-06-2612-77/+68
| | | | llvm-svn: 306344
* [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-06-2618-226/+354
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 306341
* [Coverage] Improve readability by using a struct. NFC.Vedant Kumar2017-06-262-24/+30
| | | | llvm-svn: 306340
* reverting 306331.Ayal Zaks2017-06-261-293/+286
| | | | | | Causes TBAA metadata to be generates on reverse shuffles, investigating. llvm-svn: 306338
* [x86] add tests for missing sbb transforms; NFCSanjay Patel2017-06-261-0/+80
| | | | llvm-svn: 306337
* Enable vectorizer-maximize-bandwidth by default.Dehao Chen2017-06-2612-68/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: vectorizer-maximize-bandwidth is generally useful in terms of performance. I've tested the impact of changing this to default on speccpu benchmarks on sandybridge machines. The result shows non-negative impact: spec/2006/fp/C++/444.namd 26.84 -0.31% spec/2006/fp/C++/447.dealII 46.19 +0.89% spec/2006/fp/C++/450.soplex 42.92 -0.44% spec/2006/fp/C++/453.povray 38.57 -2.25% spec/2006/fp/C/433.milc 24.54 -0.76% spec/2006/fp/C/470.lbm 41.08 +0.26% spec/2006/fp/C/482.sphinx3 47.58 -0.99% spec/2006/int/C++/471.omnetpp 22.06 +1.87% spec/2006/int/C++/473.astar 22.65 -0.12% spec/2006/int/C++/483.xalancbmk 33.69 +4.97% spec/2006/int/C/400.perlbench 33.43 +1.70% spec/2006/int/C/401.bzip2 23.02 -0.19% spec/2006/int/C/403.gcc 32.57 -0.43% spec/2006/int/C/429.mcf 40.35 +0.27% spec/2006/int/C/445.gobmk 26.96 +0.06% spec/2006/int/C/456.hmmer 24.4 +0.19% spec/2006/int/C/458.sjeng 27.91 -0.08% spec/2006/int/C/462.libquantum 57.47 -0.20% spec/2006/int/C/464.h264ref 46.52 +1.35% geometric mean +0.29% The regression on 453.povray seems real, but is due to secondary effects as all hot functions are bit-identical with and without the flag. I started this patch to consult upstream opinions on this. It will be greatly appreciated if the community can help test the performance impact of this change on other architectures so that we can decided if this should be target-dependent. Reviewers: hfinkel, mkuper, davidxl, chandlerc Reviewed By: chandlerc Subscribers: rengolin, sanjoy, javed.absar, bjope, dorit, magabari, RKSimon, llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D33341 llvm-svn: 306336
* Fix the bug when handling shufflevector for aarch64.Dehao Chen2017-06-262-2/+28
| | | | | | | | | | | | | | Summary: This Fixes https://bugs.llvm.org/show_bug.cgi?id=33600 Reviewers: mssimpso, davidxl, Carrot Reviewed By: mssimpso Subscribers: aemerson, rengolin, sanjoy, javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D34641 llvm-svn: 306334
* RenameIndependentSubregs: Fix iterator problemMatt Arsenault2017-06-262-0/+70
| | | | | | | | | | Fixes bug 33597. Use of substituteRegister in the tied operand case messes up the register use iterator, causing some uses to be left unprocessed. llvm-svn: 306333
* Add missing forward declaration.Vassil Vassilev2017-06-261-0/+1
| | | | | | This should fix our modules builds. llvm-svn: 306332
* [LV] Changing the interface of ValueMap, NFC.Ayal Zaks2017-06-261-286/+293
| | | | | | | | | | | | Instead of providing access to the internal MapStorage holding all Values associated with a given Key, used for setting or resetting them all together, ValueMap keeps its MapStorage internal; its new interface allows getting, setting or resetting a single Value, per part or per part-and-lane. Follows the discussion in https://reviews.llvm.org/D32871. Differential Revision: https://reviews.llvm.org/D34473 llvm-svn: 306331
* [WebAssembly] Add more support for weak symbolsSam Clegg2017-06-264-0/+72
| | | | | | | | | Add weak symbol tests to MC Add symbol flags to output of `llvm-readobj -t`. Differential Revision: https://reviews.llvm.org/D34635 llvm-svn: 306330
* AArch64: legalize G_EXTRACT operations.Tim Northover2017-06-268-15/+168
| | | | | | | This is the dual problem to legalizing G_INSERTs so most of the code and testing was cribbed from there. llvm-svn: 306328
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