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* Fix PowerPC/cttz.ll to specify a cpu (and use FileCheck)Hal Finkel2013-04-011-1/+3
| | | | llvm-svn: 178472
* Add the PPC popcntw instructionHal Finkel2013-04-013-7/+13
| | | | | | | | | The popcntw instruction is available whenever the popcntd instruction is available, and performs a separate popcnt on the lower and upper 32-bits. Ignoring the high-order count, this can be used for the 32-bit input case (saving on the explicit zero extension otherwise required to use popcntd). llvm-svn: 178470
* Add support for vector data types in the LLVM interpreter.Nadav Rotem2013-04-015-7/+275
| | | | | | | Patch by: Veselov, Yuri <Yuri.Veselov@intel.com> llvm-svn: 178469
* Treat PPCISD::STFIWX like the memory opcode that it isHal Finkel2013-04-012-6/+13
| | | | | | | | | | | PPCISD::STFIWX is really a memory opcode, and so it should come after FIRST_TARGET_MEMORY_OPCODE, and we should use DAG.getMemIntrinsicNode to create nodes using it. No functionality change intended (although there could be optimization benefits from preserving the MMO information). llvm-svn: 178468
* Remove unused typedef.Duncan Sands2013-04-011-1/+0
| | | | llvm-svn: 178462
* ARM Scheduler Model: Add resources instructions, map resources in subtargetsArnold Schwaighofer2013-04-014-41/+85
| | | | | | | | | | | | | Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
* X86TTI: Add accurate costs for itofp operations, based on the actual ↵Benjamin Kramer2013-04-013-9/+106
| | | | | | instruction counts. llvm-svn: 178459
* Whitespace cleanupJoe Abbey2013-04-014-21/+21
| | | | llvm-svn: 178454
* R600: Emit native instructions for texVincent Lejeune2013-03-312-115/+197
| | | | llvm-svn: 178452
* There is no longer any need to silence this compiler warning as the warning hasDuncan Sands2013-03-311-1/+1
| | | | | | been turned off globally. llvm-svn: 178451
* Cleanup ImmToIdxMap and noImmForm in PPCRegisterInfoHal Finkel2013-03-312-20/+6
| | | | | | | | | | | ImmToIdxMap should be a DenseMap (not a std::map) because there is no ordering requirement. Also, we don't need a separate list of instructions for noImmForm in eliminateFrameIndex, because this list is essentially the complement of the keys in ImmToIdxMap. No functionality change intended. llvm-svn: 178450
* X86: Promote sitofp <8 x i16> to <8 x i32> when AVX is available.Benjamin Kramer2013-03-312-0/+7
| | | | | | A vector sext + sitofp is a lot cheaper than 8 scalar conversions. llvm-svn: 178448
* Add the PPC lfiwax instructionHal Finkel2013-03-318-22/+82
| | | | | | | | | This instruction is available on modern PPC64 CPUs, and is now used to improve the SINT_TO_FP lowering (by eliminating the need for the separate sign extension instruction and decreasing the amount of needed stack space). llvm-svn: 178446
* Cleanup PPC(64) i32 -> float/double conversionHal Finkel2013-03-316-42/+40
| | | | | | | | | | | | | | | The existing SINT_TO_FP code for i32 -> float/double conversion was disabled because it relied on broken EXTSW_32/STD_32 instruction definitions. The original intent had been to enable these 64-bit instructions to be used on CPUs that support them even in 32-bit mode. Unfortunately, this form of lying to the infrastructure was buggy (as explained in the FIXME comment) and had therefore been disabled. This re-enables this functionality, using regular DAG nodes, but only when compiling in 64-bit mode. The old STD_32/EXTSW_32 definitions (which were dead) are removed. llvm-svn: 178438
* DAGCombine: visitXOR can replace a node without returning it, bail out in ↵Benjamin Kramer2013-03-302-3/+36
| | | | | | | | that case. Fixes the crash reported in PR15608. llvm-svn: 178429
* Add start of user documentation for NVPTXJustin Holewinski2013-03-303-0/+287
| | | | | | | | Summary: This is the beginning of user documentation for the NVPTX back-end. I want to ensure I am integrating this properly into the rest of the LLVM documentation. Differential Revision: http://llvm-reviews.chandlerc.com/D600 llvm-svn: 178428
* Change '@SECREL' suffix to GAS-compatible '@SECREL32'.Benjamin Kramer2013-03-303-22/+22
| | | | | | | | | | '@SECREL' is what is used by the Microsoft assembler, but GNU as expects '@SECREL32'. With the patch, the MC-generated code works fine in combination with a recent GNU as (2.23.51.20120920 here). Patch by David Nadlinger! Differential Revision: http://llvm-reviews.chandlerc.com/D429 llvm-svn: 178427
* [docs] llvmbugs is not the place for patches.Sean Silva2013-03-301-5/+6
| | | | llvm-svn: 178426
* [docs] Annotate mailing lists with their "name".Sean Silva2013-03-301-5/+5
| | | | | | | | Nobody says "the developer's list" or "commits archive"; they always say "llvmdev" or "llvm-commits". It makes sense for our documentation to at least make that association explicitly. llvm-svn: 178425
* [docs] Reorganize mailing lists.Sean Silva2013-03-301-13/+13
| | | | | | Order them roughly by "which one should a newbie join first". llvm-svn: 178424
* [docs] Pull IRC and Mailing Lists under a new "Community" heading.Sean Silva2013-03-301-21/+29
| | | | llvm-svn: 178423
* [docs] The GEP FAQ is not "design and overview"Sean Silva2013-03-301-5/+5
| | | | llvm-svn: 178422
* [docs] Put DeveloperPolicy under "Development Process Documentation"Sean Silva2013-03-301-4/+4
| | | | llvm-svn: 178421
* Put private class into an anonmyous namespace.Benjamin Kramer2013-03-301-0/+2
| | | | llvm-svn: 178420
* [NVPTX] Remove support for SM < 2.0. This was never fully supported anyway.Justin Holewinski2013-03-3018-184/+3
| | | | llvm-svn: 178417
* [NVPTX] Add NVVMReflect pass to allow compile-time selection ofJustin Holewinski2013-03-304-0/+235
| | | | | | | | | | | | | | | | specific code paths. This allows us to write code like: if (__nvvm_reflect("FOO")) // Do something else // Do something else and compile into a library, then give "FOO" a value at kernel compile-time so the check becomes a no-op. llvm-svn: 178416
* [NVPTX] Run clang-format on all NVPTX sources.Justin Holewinski2013-03-3031-1956/+2298
| | | | | | | Hopefully this resolves any outstanding style issues and gives us an automated way of ensuring we conform to the style guidelines. llvm-svn: 178415
* Object: Turn a couple of degenerate for loops into while loops.Benjamin Kramer2013-03-301-15/+12
| | | | | | No functionality change. llvm-svn: 178413
* Implement XOR reassociation. It is based on following rules:Shuxin Yang2013-03-302-1/+476
| | | | | | | | | | | | | | | rule 1: (x | c1) ^ c2 => (x & ~c1) ^ (c1^c2), only useful when c1=c2 rule 2: (x & c1) ^ (x & c2) = (x & (c1^c2)) rule 3: (x | c1) ^ (x | c2) = (x & c3) ^ c3 where c3 = c1 ^ c2 rule 4: (x | c1) ^ (x & c2) => (x & c3) ^ c1, where c3 = ~c1 ^ c2 It reduces an application's size (in terms of # of instructions) by 8.9%. Reviwed by Pete Cooper. Thanks a lot! rdar://13212115 llvm-svn: 178409
* [mips] Add patterns for DSP indexed load instructions.Akira Hatanaka2013-03-303-13/+73
| | | | llvm-svn: 178408
* [mips] Define reg+imm load/store pattern templates.Akira Hatanaka2013-03-302-16/+18
| | | | llvm-svn: 178407
* [mips] Fix DSP instructions to have explicit accumulator register operands.Akira Hatanaka2013-03-304-243/+206
| | | | | | | Check that instruction selection can select multiply-add/sub DSP instructions from a pattern that doesn't have intrinsics. llvm-svn: 178406
* Remove unused variables.Akira Hatanaka2013-03-301-2/+0
| | | | llvm-svn: 178405
* [mips] Move the code which does dag-combine for multiply-add/sub nodes toAkira Hatanaka2013-03-304-186/+200
| | | | | | | | | derived class MipsSETargetLowering. We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16 doesn't have support for multipy-add/sub instructions. llvm-svn: 178404
* [mips] Fix definitions of multiply, multiply-add/sub and divide instructions.Akira Hatanaka2013-03-307-70/+199
| | | | | | | | | The new instructions have explicit register output operands and use table-gen patterns instead of C++ code to do instruction selection. Mips16's instructions are unaffected by this change. llvm-svn: 178403
* [mips] Remove function getFPBranchCodeFromCond. Rename invertFPCondCodeAdd.Akira Hatanaka2013-03-301-18/+7
| | | | llvm-svn: 178396
* Fix indentation.Akira Hatanaka2013-03-301-26/+26
| | | | llvm-svn: 178395
* [mips] Add mips-specific nodes which will be used to select multiply and divideAkira Hatanaka2013-03-302-0/+18
| | | | | | instructions. llvm-svn: 178394
* [mips] Implement getRepRegClassFor in MipsSETargetLowering. This function isAkira Hatanaka2013-03-301-0/+9
| | | | | | called in several places in ScheduleDAGRRList.cpp. llvm-svn: 178393
* [mips] Fix MipsSEInstrInfo::copyPhysReg, loadRegFromStack and storeRegToStackAkira Hatanaka2013-03-301-0/+18
| | | | | | to handle accumulator registers. llvm-svn: 178392
* [mips] Expand pseudo load, store and copy instructions right beforeAkira Hatanaka2013-03-301-1/+165
| | | | | | | | | callee-saved scan. The code makes use of register's scavenger's capability to spill multiple registers. llvm-svn: 178391
* [mips] Define pseudo instructions for spilling and copying accumulatorAkira Hatanaka2013-03-303-0/+26
| | | | | | registers. llvm-svn: 178390
* Use SmallVectorImpl instead of SmallVector at the uses.Eric Christopher2013-03-293-18/+18
| | | | llvm-svn: 178386
* Run the ObjCARCContract pass for LTO. <rdar://problem/13538084>Bob Wilson2013-03-291-0/+5
| | | | llvm-svn: 178385
* Updated test0 of retain-not-declared.ll to reflect the fact that ↵Michael Gottesman2013-03-291-2/+2
| | | | | | | | | | objc-arc-expand runs before objc-arc/objc-arc-contract. Specifically, objc-arc-expand will make sure that the objc_retainAutoreleasedReturnValue, objc_autoreleaseReturnValue, and ret will all have %call as an argument. llvm-svn: 178382
* SmallVector and SmallPtrSet allocations now power-of-two aligned.Jean-Luc Duprat2013-03-294-33/+81
| | | | | | This time tested on both OSX and Linux. llvm-svn: 178377
* [docs] The STL "binary search" has a non-obvious name.Sean Silva2013-03-291-1/+3
| | | | | | | | | | | | | std::lower_bound is the canonical "binary search" in the STL (std::binary_search generally is not what you want). The name actually makes a lot of sense (and also has a beautiful symmetry with the std::upper_bound algorithm). The name is nonetheless non-obvious. Also, remove mention of "radix search". It's not even clear how that would work in the context of a sorted vector. AFAIK "radix search" only makes sense when you have a trie-like data structure. llvm-svn: 178376
* Exclude the X86/complex-fca.ll test at it probably wasn't supposed to work ↵Timur Iskhodzhanov2013-03-291-0/+3
| | | | | | on Windows llvm-svn: 178375
* Add clang.arc.used to ModuleHasARC so ARC always runs if said call is ↵Michael Gottesman2013-03-292-1/+18
| | | | | | | | | | present in a module. clang.arc.used is an interesting call for ARC since ObjCARCContract needs to run to remove said intrinsic to avoid a linker error (since the call does not exist). llvm-svn: 178369
* Hexagon: Add emitFrameIndexDebugValue function to emit debug information.Jyotsna Verma2013-03-292-0/+14
| | | | llvm-svn: 178368
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