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* Simplify.Devang Patel2011-07-141-13/+3
| | | | llvm-svn: 135127
* Don't emit a bit test if there is only one case the test can yield false. A ↵Benjamin Kramer2011-07-143-10/+33
| | | | | | simple SETNE is sufficient. llvm-svn: 135126
* Simplify and delay extracting DebugLoc elements, scope and InlinedAt, as ↵Devang Patel2011-07-144-19/+34
| | | | | | much as possible. llvm-svn: 135124
* Add a dag combine pattern for folding C2-(A+C1) -> (C2-C1)-AEric Christopher2011-07-141-2/+10
| | | | | | Fixes rdar://9761830 llvm-svn: 135123
* Revert r135121 which broke a gcc-4.2 builder.Jakob Stoklund Olesen2011-07-143-70/+11
| | | | llvm-svn: 135122
* Count references to interference cache entries.Jakob Stoklund Olesen2011-07-143-11/+70
| | | | | | | | | | | | | | | | | Each InterferenceCache::Cursor instance references a cache entry. A non-zero reference count guarantees that the entry won't be reused for a new register. This makes it possible to have multiple live cursors examining interference for different physregs. The total number of live cursors into a cache must be kept below InterferenceCache::getMaxCursors(). Code generation should be unaffected by this change, and it doesn't seem to affect the cache replacement strategy either. llvm-svn: 135121
* Fix up assertion in r135018 so it doesn't trigger on 32-bit; when we're in ↵Eli Friedman2011-07-141-1/+2
| | | | | | 32-bit, it doesn't matter whether the operation overflows because the computed address is not wider than the immediate. llvm-svn: 135120
* ARM tests for EOR instruction parsing and encoding.Jim Grosbach2011-07-141-0/+57
| | | | llvm-svn: 135119
* Simplify. Compile unit check inside hasValidLocation() did not add any value.Devang Patel2011-07-141-26/+10
| | | | llvm-svn: 135118
* Remove duplicate tests.Jim Grosbach2011-07-141-24/+0
| | | | llvm-svn: 135117
* ARM Assembler support for DSB instruction.Jim Grosbach2011-07-142-0/+33
| | | | | | Add instalias for default 'sy' option. Add tests. llvm-svn: 135116
* Reapply r135074 and r135080 with a fix.Jakob Stoklund Olesen2011-07-142-28/+39
| | | | | | | | | | The cache entry referenced by the best split candidate could become clobbered by an unsuccessful candidate. The correct fix here is to use reference counts on the cache entries. Coming up. llvm-svn: 135113
* DMB instalias needs the same predicate as the instruction.Jim Grosbach2011-07-141-1/+1
| | | | llvm-svn: 135112
* Fix typo in DEBUG message.Devang Patel2011-07-141-2/+2
| | | | llvm-svn: 135111
* Add DEBUG messages.Devang Patel2011-07-141-0/+5
| | | | llvm-svn: 135110
* ARM Assembler support for DMB instruction.Jim Grosbach2011-07-134-24/+38
| | | | | | | | Flesh out the options supported for the instruction. Shuffle tests a bit and add entries for the rest of the options. Add an alias to handle the default operand of "sy". llvm-svn: 135109
* Update comments. These are for assembler, too.Jim Grosbach2011-07-131-3/+2
| | | | llvm-svn: 135107
* Add a target-indepedent entry to MCInstrDesc to describe the encoded size of ↵Owen Anderson2011-07-1311-249/+230
| | | | | | an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
* Add code to handle a "frameless" unwind stack.Bill Wendling2011-07-131-13/+55
| | | | | | | The frameless unwind stack has a special encoding, the algorithm for which is in "permuteEncode". llvm-svn: 135103
* ARM Assembler support for DBG instruction.Jim Grosbach2011-07-134-5/+22
| | | | | | Add range checking and testing for parsing and encoding of DBG instruction. llvm-svn: 135102
* We already support 256-bit packed ADD, SUB, DIV, MUL. Add testcases.Bruno Cardoso Lopes2011-07-131-0/+116
| | | | llvm-svn: 135099
* ARM parsing and encoding tests for CMN/CMP.Jim Grosbach2011-07-131-0/+59
| | | | llvm-svn: 135098
* struct Init -> class InitDavid Greene2011-07-134-5/+6
| | | | | | | Rename struct Init to class Init for consistency and in preparation for making Init a FoldingSetNode. llvm-svn: 135097
* Revert r135074 and r135080. They broke clamscan.Jakob Stoklund Olesen2011-07-132-34/+28
| | | | llvm-svn: 135096
* Shuffle ARM assembly tests a bit.Jim Grosbach2011-07-132-10/+22
| | | | llvm-svn: 135095
* Revert 135093. Think-o.Jim Grosbach2011-07-131-2/+2
| | | | llvm-svn: 135094
* Correct range for thumb co-processor immediateJim Grosbach2011-07-131-2/+2
| | | | llvm-svn: 135093
* Range checking for CDP[2] immediates.Jim Grosbach2011-07-137-12/+79
| | | | llvm-svn: 135092
* Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A moreBruno Cardoso Lopes2011-07-134-64/+82
| | | | | | | general version of X86ISD::ANDNP also opened the room for a little bit of refactoring. llvm-svn: 135088
* The target specific node PANDN name is misleading. That happens becauseBruno Cardoso Lopes2011-07-134-12/+12
| | | | | | | it's later selected to a ANDNPD/ANDNPS instruction instead of the PANDN instruction. Rename it. llvm-svn: 135087
* Cleanup Thumb co-processor instructions a bit.Jim Grosbach2011-07-131-79/+35
| | | | | | Combine redundant base classes and such. No indended functional change. llvm-svn: 135085
* Make sure we don't combine a large displacement and a frame index in the ↵Eli Friedman2011-07-132-8/+45
| | | | | | | | same addressing mode on x86-64. It can overflow, leading to a crash/miscompile. <rdar://problem/9763308> llvm-svn: 135084
* Parameterize away the ARM T1Cop class.Jim Grosbach2011-07-132-13/+12
| | | | llvm-svn: 135082
* Fix predicates for Thumb co-processor instructions.Jim Grosbach2011-07-135-119/+110
| | | | | | | They're all Thumb2 only, not just some of them. More refactoring cleanup coming. llvm-svn: 135081
* Only keep the global split candidates that work out.Jakob Stoklund Olesen2011-07-131-12/+15
| | | | | | | | | Some pysical registers create split solutions that would spill anywhere. They should not even be considered in future multi-way global splits. This does not affect code generation (yet). llvm-svn: 135080
* Refactor out checking for displacements on x86-64 addressing modes. No ↵Eli Friedman2011-07-131-46/+34
| | | | | | | | functionality change. Refactoring in preparation for an additional safety check in FoldOffsetIntoAddress. Part of <rdar://problem/9763308>. llvm-svn: 135079
* Testcases for ARM assembly BX/BXJ instructions.Jim Grosbach2011-07-131-2/+24
| | | | llvm-svn: 135078
* Fix encoding for ARM BXJ instruction.Jim Grosbach2011-07-131-3/+5
| | | | llvm-svn: 135077
* Fix encoding of predicate bits on ARM BX_pred.Jim Grosbach2011-07-131-3/+2
| | | | llvm-svn: 135076
* Move the InterferenceCache cursor into the GlobalSplitCand struct.Jakob Stoklund Olesen2011-07-132-20/+23
| | | | | | | This is in preparation of supporting multiple global split candidates in a single live range split operation. llvm-svn: 135074
* Testcases for ARM assembly BLX/BL instructions.Jim Grosbach2011-07-131-0/+17
| | | | llvm-svn: 135072
* Range checking for 16-bit immediates in ARM assembly.Jim Grosbach2011-07-134-5/+25
| | | | llvm-svn: 135071
* Revert r135042. As Chris pointed out, it had no effect, and was based onJay Foad2011-07-131-5/+0
| | | | | | a complete misunderstanding of the code. llvm-svn: 135070
* Fix up TargetLoweringObjectFile ctors to properly initialize fields.Evan Cheng2011-07-133-29/+70
| | | | llvm-svn: 135068
* Give the ARM BKPT instruction the right operand type.Jim Grosbach2011-07-132-5/+5
| | | | | | The immediate is of limited range and the operand type should reflect that. llvm-svn: 135066
* Change test case, one that actually failed before my commit.Evan Cheng2011-07-131-1/+6
| | | | llvm-svn: 135064
* Add tests for ARM parsing of 'BKPT' instruction.Jim Grosbach2011-07-132-2/+10
| | | | llvm-svn: 135063
* Fix copy-pasto.Jim Grosbach2011-07-131-1/+1
| | | | llvm-svn: 135062
* Add tests for ARM parsing of 'BIC' instruction.Jim Grosbach2011-07-131-0/+58
| | | | llvm-svn: 135061
* Add some FIXMEs.Jim Grosbach2011-07-131-0/+16
| | | | | | | Keeping the instructions in alphabetical order, just like in the ARM ARM. Adding FIXMEs for skipped instructions when adding tests out of order. llvm-svn: 135060
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