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* DataExtractor: Fix integer truncation issues in LEB128 extraction.Benjamin Kramer2012-08-202-3/+12
| | | | llvm-svn: 162201
* Forget to add testcase for r162195. Sorry.Stepan Dyatkovskiy2012-08-201-0/+10
| | | | llvm-svn: 162196
* Fixed DAGCombiner bug (found and localized by James Malloy):Stepan Dyatkovskiy2012-08-201-3/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DAGCombiner tries to optimise a BUILD_VECTOR by checking if it consists purely of get_vector_elts from one or two source vectors. If so, it either makes a concat_vectors node or a shufflevector node. However, it doesn't check the element type width of the underlying vector, so if you have this sequence: Node0: v4i16 = ... Node1: i32 = extract_vector_elt Node0 Node2: i32 = extract_vector_elt Node0 Node3: v16i8 = BUILD_VECTOR Node1, Node2, ... It will attempt to: Node0: v4i16 = ... NewNode1: v16i8 = concat_vectors Node0, ... Where this is actually invalid because the element width is completely different. This causes an assertion failure on DAG legalization stage. Fix: If output item type of BUILD_VECTOR differs from input item type. Make concat_vectors based on input element type and then bitcast it to the output vector type. So the case described above will transformed to: Node0: v4i16 = ... NewNode1: v8i16 = concat_vectors Node0, ... NewNode2: v16i8 = bitcast NewNode1 llvm-svn: 162195
* Remove FMA3 intrinsic instructions in favor of patterns.Craig Topper2012-08-202-94/+146
| | | | llvm-svn: 162194
* Use correct intrinsic for 256-bit VFMSUBADDPS.Craig Topper2012-08-201-1/+1
| | | | llvm-svn: 162193
* Remove trailing white space and tab characters. No functional change.Craig Topper2012-08-191-33/+33
| | | | llvm-svn: 162192
* When unsafe math is used, we can use commutative FMAX and FMIN. In some casesNadav Rotem2012-08-195-51/+91
| | | | | | | | | | | | | | | | | | | this allows for better code generation. Added a new DAGCombine transformation to convert FMAX and FMIN to FMANC and FMINC, which are commutative. For example: movaps %xmm0, %xmm1 movsd LC(%rip), %xmm0 minsd %xmm1, %xmm0 becomes: minsd LC(%rip), %xmm0 llvm-svn: 162187
* Fabs folding is implemented.Benjamin Kramer2012-08-191-5/+0
| | | | llvm-svn: 162186
* InstCombine: Fix a crasher when encountering a function pointer.Benjamin Kramer2012-08-182-1/+9
| | | | llvm-svn: 162180
* Remove the CAND/COR/CXOR custom ISD nodes and their select code.Jakob Stoklund Olesen2012-08-183-174/+0
| | | | | | | These nodes are no longer needed because the peephole pass can fold CMOV+AND into ANDCC etc. llvm-svn: 162179
* Remove virtual from many methods. These methods replace methods in the base ↵Craig Topper2012-08-181-38/+40
| | | | | | class, but the base class methods aren't virtual so it just increased call overhead. llvm-svn: 162178
* Also combine zext/sext into selects for ARM.Jakob Stoklund Olesen2012-08-182-47/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This turns common i1 patterns into predicated instructions: (add (zext cc), x) -> (select cc (add x, 1), x) (add (sext cc), x) -> (select cc (add x, -1), x) For a function like: unsigned f(unsigned s, int x) { return s + (x>0); } We now produce: cmp r1, #0 it gt addgt.w r0, r0, #1 Instead of: movs r2, #0 cmp r1, #0 it gt movgt r2, #1 add r0, r2 llvm-svn: 162177
* Also pass logical ops to combineSelectAndUse.Jakob Stoklund Olesen2012-08-182-17/+50
| | | | | | | | | | | | | | | | Add these transformations to the existing add/sub ones: (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) (or (select cc, 0, c), x) -> (select cc, x, (or, x, c)) (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c)) The selects can then be transformed to a single predicated instruction by peephole. This transformation will make it possible to eliminate the ISD::CAND, COR, and CXOR custom DAG nodes. llvm-svn: 162176
* Remove overly conservative hasOneUse check, this always expands into a ↵Benjamin Kramer2012-08-181-1/+1
| | | | | | single IR instruction. llvm-svn: 162175
* InstCombine: Add a couple of fabs identities for comparing with 0.0.Benjamin Kramer2012-08-182-0/+121
| | | | llvm-svn: 162174
* SimplifyLibcalls: Add fabs and trunc to the list of libcalls that are safe ↵Benjamin Kramer2012-08-182-0/+27
| | | | | | to shrink from double to float. llvm-svn: 162173
* Reapply r162160 with a fix: Optimize Arith->Trunc->SETCC sequence to allow ↵Nadav Rotem2012-08-183-17/+107
| | | | | | better compare/branch code. llvm-svn: 162172
* fp16-to-fp32 conversion instructions are available in Thumb mode as well.Anton Korobeynikov2012-08-181-4/+4
| | | | | | Make sure the generic pattern is used. llvm-svn: 162170
* Refactor code a bit to reduce number of calls in the final compiled code. No ↵Craig Topper2012-08-181-134/+144
| | | | | | functional change intended. llvm-svn: 162166
* Reorder initialization list to silence -WreorderCraig Topper2012-08-181-2/+2
| | | | llvm-svn: 162165
* Revert r162160 because it made a few buildbots fail.Nadav Rotem2012-08-183-90/+8
| | | | llvm-svn: 162164
* The X86 backend has a number of optimizations for SETCC nodes which useNadav Rotem2012-08-183-8/+90
| | | | | | | | | | | | | | | | | | | | | arithmetic instructions. However, when small data types are used, a truncate node appears between the SETCC node and the arithmetic operation. This patch adds support for this pattern. Before: xorl %esi, %edi testb %dil, %dil setne %al ret After: xorb %dil, %sil setne %al ret rdar://12081007 llvm-svn: 162160
* Make atomic load and store of pointers work. Tighten verification of atomic ↵Eli Friedman2012-08-173-2/+56
| | | | | | | | | operations so other unexpected operations don't slip through. Based on patch by Logan Chien. PR11786/PR13186. llvm-svn: 162146
* Fix undefined behavior (binding a reference to a dereferenced null pointer) ifRichard Smith2012-08-171-1/+1
| | | | | | SSAUpdater was created and destroyed without being initialized. llvm-svn: 162137
* Add MipsELFWriterInfo.{h,cpp}.Akira Hatanaka2012-08-172-0/+151
| | | | llvm-svn: 162136
* Correct MCJIT functionality for MIPS32 architecture.Akira Hatanaka2012-08-179-8/+137
| | | | | | | | | | No new tests are added. All tests in ExecutionEngine/MCJIT that have been failing pass after this patch is applied (when "make check" is done on a mips board). Patch by Petar Jovanovic. llvm-svn: 162135
* Implement stack protectors for structures with character arrays in them.Bill Wendling2012-08-171-15/+40
| | | | | | <rdar://problem/10545247> llvm-svn: 162131
* Avoid folding ADD instructions with FI operands.Jakob Stoklund Olesen2012-08-172-0/+14
| | | | | | | | | PEI can't handle the pseudo-instructions. This can be removed when the pseudo-instructions are replaced by normal predicated instructions. Fixes PR13628. llvm-svn: 162130
* Add stub methods for mips assembly matcher. Akira Hatanaka2012-08-1710-7/+104
| | | | | | Patch by Vladimir Medic. llvm-svn: 162124
* MemoryBuiltins: Properly guard ObjectSizeOffsetVisitor against cycles in the IR.Benjamin Kramer2012-08-173-20/+17
| | | | | | | | | | The previous fix only checked for simple cycles, use a set to catch longer cycles too. Drop the broken check from the ObjectSizeOffsetEvaluator. The BoundsChecking pass doesn't have to deal with invalid IR like InstCombine does. llvm-svn: 162120
* Change the `linker_private_weak_def_auto' linkage to `linkonce_odr_auto_hide' toBill Wendling2012-08-1717-62/+59
| | | | | | | | | | | | | | | | | | | | make it more consistent with its intended semantics. The `linker_private_weak_def_auto' linkage type was meant to automatically hide globals which never had their addresses taken. It has nothing to do with the `linker_private' linkage type, which outputs the symbols with a `l' (ell) prefix among other things. The intended semantic is more like the `linkonce_odr' linkage type. Change the name of the linkage type to `linkonce_odr_auto_hide'. And therefore changing the semantics so that it produces the correct output for the linker. Note: The old linkage name `linker_private_weak_def_auto' will still parse but is not a synonym for `linkonce_odr_auto_hide'. This should be removed in 4.0. <rdar://problem/11754934> llvm-svn: 162114
* Assert that dominates is not given a multiple edge. Finding out if we haveRafael Espindola2012-08-173-1/+17
| | | | | | | | | | | | | multiple edges between two blocks is linear. If the caller is iterating all edges leaving a BB that would be a square time algorithm. It is more efficient to have the callers handle that case. Currently the only callers are: * GVN: already avoids the multiple edge case. * Verifier: could only hit this assert when looking at an invalid invoke. Since it already rejects the invoke, just avoid computing the dominance for it. llvm-svn: 162113
* Add comment, clean up code. No functional change.Jakob Stoklund Olesen2012-08-171-30/+39
| | | | llvm-svn: 162107
* TargetLowering: Use the large shift amount during legalize types. The ↵Benjamin Kramer2012-08-172-3/+35
| | | | | | legalizer may call us with an overly large type. llvm-svn: 162101
* Use standard pattern for iterate+erase.Jakob Stoklund Olesen2012-08-171-9/+2
| | | | | | | | | Increment the MBB iterator at the top of the loop to properly handle the current (and previous) instructions getting erased. This fixes PR13625. llvm-svn: 162099
* Guard MemoryBuiltins against self-looping GEPs, which can occur in ↵Benjamin Kramer2012-08-172-0/+21
| | | | | | | | unreachable code due to constant propagation. Fixes PR13621. llvm-svn: 162098
* Fix broken check lines.Benjamin Kramer2012-08-1710-28/+27
| | | | | | | | I really need to find a way to automate this, but I can't come up with a regex that has no false positives while handling tricky cases like custom check prefixes. llvm-svn: 162097
* Implement NEON domain switching for scalar <-> S-register vmovs on ARMTim Northover2012-08-172-47/+129
| | | | llvm-svn: 162094
* Insertion of NoFolder functions to avoid ambiguous overload warnings or ↵Jin-Gu Kang2012-08-171-0/+12
| | | | | | errors about whether to convert Idx to ArrayRef<Constant *> or ArrayRef<Value *> like ConstantFolder and TargetFolder. llvm-svn: 162090
* Use nested switch to select arguments to reduce calls to EmitPCMP.Craig Topper2012-08-171-5/+20
| | | | llvm-svn: 162089
* Make ReplaceATOMIC_BINARY_64 a static function. Use a nested switch to ↵Craig Topper2012-08-172-19/+30
| | | | | | reduce to only a single call to it thus allowing it to be inlined by the compiler. llvm-svn: 162088
* Test commit.Pranav Bhandarkar2012-08-171-1/+1
| | | | | | | include/llvm/IntrinsicsHexagon.td: Hexagon_Intrinsic is the base class for all Hexagon intrinsics and not altivec intrinsics. llvm-svn: 162087
* Remove unnecessary include of ARMGenInstrInfo.inc.Craig Topper2012-08-171-1/+0
| | | | llvm-svn: 162086
* Declare some for loop indices inside the for loop statement.Craig Topper2012-08-171-20/+13
| | | | llvm-svn: 162085
* Fix up indentation of outputted decode function for readability.Craig Topper2012-08-171-8/+8
| | | | llvm-svn: 162082
* lit: Show actually created count of threads. The incorrect threads count is ↵NAKAMURA Takumi2012-08-171-3/+3
| | | | | | | | printed if the number of tests are less than the number of default threads. Thanks to Vinson Lee, reported in PR13620. llvm-svn: 162078
* Flatten the aligned-char-array utility template to be a directlyChandler Carruth2012-08-173-134/+133
| | | | | | | templated union at the request of Richard Smith. This makes it substantially easier to type. =] llvm-svn: 162072
* Add ADD and SUB to the predicable ARM instructions.Jakob Stoklund Olesen2012-08-166-21/+86
| | | | | | | | | | It is not my plan to duplicate the entire ARM instruction set with predicated versions. We need a way of representing predicated instructions in SSA form without requiring a separate opcode. Then the pseudo-instructions can go away. llvm-svn: 162061
* Handle ARM MOVCC optimization in PeepholeOptimizer.Jakob Stoklund Olesen2012-08-165-53/+73
| | | | | | Use the target independent select analysis hooks. llvm-svn: 162060
* Add an MCID::Select flag and TII hooks for optimizing selects.Jakob Stoklund Olesen2012-08-168-16/+89
| | | | | | | | | | | | Select instructions pick one of two virtual registers based on a condition, like x86 cmov. On targets like ARM that support predication, selects can sometimes be eliminated by predicating the instruction defining one of the operands. Teach PeepholeOptimizer to recognize select instructions, and ask the target to optimize them. llvm-svn: 162059
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