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* [X86][AVX512] Tidied up VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 comment ↵Simon Pilgrim2016-06-111-35/+17
| | | | | | | | generation Now matches other shuffles llvm-svn: 272464
* Try a bit harder to remove the signed and unsigned comparison warning.Chandler Carruth2016-06-111-1/+1
| | | | | | Hopefully this time it actually works and stays away. llvm-svn: 272463
* Use a two-level cast through an intptr_t, and make them C-style casts.Chandler Carruth2016-06-111-1/+1
| | | | | | | | | This shouldn't have any functional difference, but it appears to be the pattern used for other methods on DynamicLibrary, and it should avoid the -Wpedantic warning on one of the build bots about the direct reinterpret_cast. llvm-svn: 272461
* Add a using declaration so that the overrides don't hide some of theChandler Carruth2016-06-111-0/+1
| | | | | | | | | base class methods. This was caught by GCC's -Woverloaded-virtual, not sure why it wasn't caught by Clang's. =/ llvm-svn: 272460
* Compare to an unsigned literal to avoid a -Wsign-compare warning.Chandler Carruth2016-06-111-1/+1
| | | | llvm-svn: 272459
* Use const_cast to cast away constness. This silences a warning.Chandler Carruth2016-06-111-1/+1
| | | | llvm-svn: 272458
* DebugInfoPDBTests:MappedBlockStreamTest.TestWriteThenRead: Avoid assigning ↵NAKAMURA Takumi2016-06-111-1/+3
| | | | | | temporary object to ArrayRef. llvm-svn: 272457
* [MCJIT] Update MCJIT and get the fibonacci example working again.Lang Hames2016-06-113-5/+12
| | | | | | | | | | MCJIT will now set the DataLayout on a module when it is added to the JIT, rather than waiting until it is codegen'd, and the runFunction method will finalize the module containing the function to be run before running it. The fibonacci example has been updated to include and link against MCJIT. llvm-svn: 272455
* [AVX512] Add support for lowering v32i16 shuffles with repeated lanes. This ↵Craig Topper2016-06-112-1/+40
| | | | | | allows us to create 512-bit PSHUFLW/PSHUFHW. llvm-svn: 272450
* [AVX512] No need to check for BWI being enabled before lowering v32i16 and ↵Craig Topper2016-06-111-9/+2
| | | | | | v64i8 shuffles. If we get this far the types are already legal which means BWI must be enabled. llvm-svn: 272449
* LiveIntervalAnalysis: findLastUseBefore() must ignore undef uses.Matthias Braun2016-06-112-1/+27
| | | | | | | | | | undef uses are no real uses of a register and must be ignored by findLastUseBefore() so that handleMove() does not produce invalid live intervals in some cases. This fixed http://llvm.org/PR28083 llvm-svn: 272446
* [esan|cfrag] Handle complex GEP instr in the cfrag toolQin Zhao2016-06-102-35/+80
| | | | | | | | | | | | | | | | Summary: Iterates all (except the first and the last) operands within each GEP instruction for instrumentation. Adds test struct_field_gep.ll. Reviewers: aizatsky Subscribers: vitalybuka, zhaoqin, kcc, eugenis, bruening, llvm-commits Differential Revision: http://reviews.llvm.org/D21242 llvm-svn: 272442
* Try again to fix this endianness issue.Zachary Turner2016-06-101-17/+15
| | | | llvm-svn: 272440
* Don't try to rotate a loop more than once - we never do this anyway.Michael Zolotukhin2016-06-101-14/+10
| | | | | | | | | | | | | | | | | | | | | Summary: I can't find a case where we can rotate a loop more than once, and it looks like we never do this. To rotate a loop following conditions should be met: 1) its header should be exiting 2) its latch shouldn't be exiting But after the first rotation the header becomes the new latch, so this condition can never be true any longer. Tested on with an assert on LNT testsuite and make check. Reviewers: hfinkel, sanjoy Subscribers: sebpop, sanjoy, llvm-commits, mzolotukhin Differential Revision: http://reviews.llvm.org/D20181 llvm-svn: 272439
* [pdb] Fix issues with pdb writing.Zachary Turner2016-06-102-2/+5
| | | | | | | | | This fixes an alignment issue by forcing all cached allocations to be 8 byte aligned, and also fixes an issue arising on big endian systems by writing ulittle32_t's instead of uint32_t's in the test. llvm-svn: 272437
* MemorySSA: fix memory access local dominance function for live on entrySebastian Pop2016-06-101-0/+15
| | | | | | | | | A memory access defined on function entry cannot be locally dominated by another memory access. The patch was split from http://reviews.llvm.org/D19338 which exposes the problem. Differential Revision: http://reviews.llvm.org/D21039 llvm-svn: 272436
* [STLExtras] Introduce and use llvm::count_if; NFCSanjoy Das2016-06-104-27/+25
| | | | | | (This is split out from was D21115) llvm-svn: 272435
* [IRTranslator] Support the translation of or.Quentin Colombet2016-06-102-0/+25
| | | | | | Now or instructions get translated into G_OR. llvm-svn: 272433
* [IRTranslator] Rework the comments for the methods to translate.Quentin Colombet2016-06-101-33/+35
| | | | | | NFC. llvm-svn: 272432
* [IRTranslator] Refactor to expose a translateBinaryOp method.Quentin Colombet2016-06-102-4/+12
| | | | | | | | This method will be used for every binary operation. NFC. llvm-svn: 272431
* [AArch64] Move comments closer to relevant check. NFC.Chad Rosier2016-06-101-6/+4
| | | | llvm-svn: 272430
* [AArch64] Refactor a check earlier. NFC.Chad Rosier2016-06-101-12/+18
| | | | llvm-svn: 272429
* [x86] enable bitcasted fabs/fneg transformsSanjay Patel2016-06-102-4/+6
| | | | | | | The vector cases don't change because we already have folds in X86ISelLowering to look through and remove bitcasts. llvm-svn: 272427
* [CodeGen] Fix PrologEpilogInserter to avoid duplicate allocation of SEH structsEtienne Bergeron2016-06-101-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When stack-protection is activated and WinEH exceptions is used, the EHRegNode (exception handling registration) is allocated twice on the stack. This was not breaking anything except loosing space on the stack. ``` D:\src\llvm\examples>llc exc2.ll -debug-only=pei alloc FI(0) at SP[-24] alloc FI(1) at SP[-48] <<-- Allocated alloc FI(1) at SP[-72] <<-- Allocated twice!? alloc FI(2) at SP[-76] alloc FI(4) at SP[-80] alloc FI(3) at SP[-84] ``` Reviewers: rnk, majnemer Subscribers: chrisha, llvm-commits Differential Revision: http://reviews.llvm.org/D21188 llvm-svn: 272426
* Remove a few gendered pronouns.Nico Weber2016-06-103-3/+3
| | | | llvm-svn: 272422
* Disable MSan-hostile loop unswitching.Evgeniy Stepanov2016-06-101-0/+18
| | | | | | | | | | | | | Loop unswitching may cause MSan false positive when the unswitch condition is not guaranteed to execute. This is very similar to ASan and TSan special case in llvm::isSafeToSpeculativelyExecute (they don't like speculative loads and stores), but for branch instructions. This is a workaround for PR28054. llvm-svn: 272421
* Move isGuaranteedToExecute out of LICM.Evgeniy Stepanov2016-06-103-67/+71
| | | | | | | Also rename LICMSafetyInfo to LoopSafetyInfo. Both will be used in LoopUnswitch in a separate change. llvm-svn: 272420
* [SystemZ] Support Compare and TrapsZhan Jun Liau2016-06-1012-44/+776
| | | | | | | | | | | | Support and generate Compare and Traps like CRT, CIT, etc. Support Trap as legal DAG opcodes and generate "j .+2" for them by default. Add support for Conditional Traps and use the If Converter to convert them into the corresponding compare and trap opcodes. Differential Revision: http://reviews.llvm.org/D21155 llvm-svn: 272419
* AMDGPU/SI: Don't use fixup_si_rodata for scratch rsrc relocationsTom Stellard2016-06-103-3/+11
| | | | | | | | | | | | | | | Summary: We need to set the fixup type to FK_Data_4 for the SCRATCH_RSRC_DWORD[01] symbols, since these require absolute relocations, and fixup_si_rodata is for relative relocations. Reviewers: arsenm, kzhuravl Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: http://reviews.llvm.org/D21153 llvm-svn: 272417
* Move CodeGen test from Generic to X86 specific directoryMehdi Amini2016-06-101-0/+0
| | | | llvm-svn: 272416
* Interprocedural Register Allocation (IPRA): add a Transformation PassMehdi Amini2016-06-105-0/+172
| | | | | | | | | | | | Adds a MachineFunctionPass that scans the body to find calls, and update the register mask with the one saved by the RegUsageInfoCollector analysis in PhysicalRegisterUsageInfo. Patch by Vivek Pandya <vivekvpandya@gmail.com> Differential Revision: http://reviews.llvm.org/D21180 llvm-svn: 272414
* [x86] add test for PR28044Sanjay Patel2016-06-101-0/+62
| | | | llvm-svn: 272411
* Add a period. NFC.Chad Rosier2016-06-101-1/+1
| | | | llvm-svn: 272410
* Fix whitespace. NFC.Chad Rosier2016-06-101-1/+1
| | | | llvm-svn: 272409
* test: split test into two filesSaleem Abdulrasool2016-06-102-38/+39
| | | | | | | Split up the test cases into two inputs as per post-commit review comments from Renato. NFC. llvm-svn: 272408
* [X86] Add costs for SSE zext/sext to v4i64 to TTIMichael Kuperstein2016-06-103-0/+96
| | | | | | | | | The costs are somewhat hand-wavy, but should be much closer to the truth than what we get from BasicTTI. Differential Revision: http://reviews.llvm.org/D21156 llvm-svn: 272406
* Interprocedural Register Allocation (IPRA) AnalysisMehdi Amini2016-06-1012-0/+383
| | | | | | | | | | | | | | | | | | | | | | | Add an option to enable the analysis of MachineFunction register usage to extract the list of clobbered registers. When enabled, the CodeGen order is changed to be bottom up on the Call Graph. The analysis is split in two parts, RegUsageInfoCollector is the MachineFunction Pass that runs post-RA and collect the list of clobbered registers to produce a register mask. An immutable pass, RegisterUsageInfo, stores the RegMask produced by RegUsageInfoCollector, and keep them available. A future tranformation pass will use this information to update every call-sites after instruction selection. Patch by Vivek Pandya <vivekvpandya@gmail.com> Differential Revision: http://reviews.llvm.org/D20769 llvm-svn: 272403
* [AArch64] Add preferred alignments for Exynos M1Evandro Menezes2016-06-103-2/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D21203 llvm-svn: 272400
* [Hexagon] Remove incorrect offset scalingKrzysztof Parzyszek2016-06-101-4/+2
| | | | llvm-svn: 272399
* [x86] fix test attributes and autogenerate checksSanjay Patel2016-06-101-37/+50
| | | | llvm-svn: 272398
* [x86] add missing tests for fcmp ueq/oneSanjay Patel2016-06-101-0/+212
| | | | | | | | | | | | Somehow, the codegen logic for these sequences has gone completely untested until now (note the 2 compare instructions generated per test). There's also an *Intel* AVX optimization opportunity exposed in these cases and the existing tests. Intel's (but not AMD's) AVX spec shows that extra FP predicates were added, so a single comparison should always be sufficient, and operand commutation should never be necessary. llvm-svn: 272397
* [x86] regenerate checksSanjay Patel2016-06-101-184/+309
| | | | llvm-svn: 272396
* Reapply "[TTI] Refine default cost for interleaved load groups with gaps"Matthew Simpson2016-06-102-0/+87
| | | | | | | | This reapplies commit r272385 with a fix. The build was failing when compiled with gcc, but not with clang. With the fix, we now get the data layout from the current TTI implementation, which will hopefully solve the issue. llvm-svn: 272395
* Test commitRoman Shirokiy2016-06-101-3/+3
| | | | llvm-svn: 272393
* [X86][SSE] Added target shuffle combine tests for byte shift/rotates ↵Simon Pilgrim2016-06-101-0/+50
| | | | | | (PSLLDQ/PSRLDQ/PALIGNR) llvm-svn: 272392
* Revert "[TTI] Refine default cost for interleaved load groups with gaps"Matthew Simpson2016-06-102-86/+0
| | | | | | | This reverts commit r272385. This commit broke the build. I'm temporarily reverting to investigate. llvm-svn: 272391
* [TTI] Refine default cost for interleaved load groups with gapsMatthew Simpson2016-06-102-0/+86
| | | | | | | | | | | | This patch refines the default cost for interleaved load groups having gaps. If a load group has gaps, the legalized instructions corresponding to the unused elements will be dead. Thus, we don't need to account for them in the cost model. Instead, we only need to account for the fraction of legalized loads that will actually be used. Differential Revision: http://reviews.llvm.org/D20873 llvm-svn: 272385
* [AMDGPU] AsmParser: Support for sext() modifier in SDWA. Some code cleaning ↵Sam Kolton2016-06-106-263/+362
| | | | | | | | | | | | | | | | | | in AMDGPUOperand. Summary: sext() modifier is supported in SDWA instructions only for integer operands. Spec is unclear should integer operands support abs and neg modifiers with sext - for now they are not supported. Renamed InputModsWithNoDefault to FloatInputMods. Added SextInputMods for operands that support sext() modifier. Added AMDGPUOperand::Modifier struct to handle register and immediate modifiers. Code cleaning in AMDGPUOperand class: organize method in groups (render-, predicate-methods...). Reviewers: vpykhtin, artem.tamazov, tstellarAMD Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D20968 llvm-svn: 272384
* [X86][AVX512] Added VPSLLDQ/VPSRLDQ memory fold testsSimon Pilgrim2016-06-101-12/+44
| | | | | | | | | | Memory operand is new for AVX512 (SSE/AVX2 didn't support it). Also dropped the 'mask' from the tests (VPSLLDQ/VPSRLDQ don't support masked operations). Regenerated VPALIGNR test now that the shuffle comments work llvm-svn: 272383
* Fix stale name in comment.Sean Silva2016-06-101-1/+1
| | | | llvm-svn: 272382
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