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* BPF: Use official ELF e_machine valueAlexei Starovoitov2016-07-158-1/+33
| | | | | | | | | The same value for EM_BPF is being propagated to glibc, elfutils, and binutils. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 275633
* [lanai] Fix build by updating calls to getLoad & getStore.Jacques Pienaar2016-07-151-9/+7
| | | | | | rL275592 removed the boolean parameters of SelectionDAG::getLoad and getStore, updating Lanai backend's calls to these functions. llvm-svn: 275631
* [pdb] Teach MsfBuilder and other classes about the Free Page Map.Zachary Turner2016-07-1512-40/+61
| | | | | | | | | | | | | | Block 1 and 2 of an MSF file are bit vectors that represent the list of blocks allocated and free in the file. We had been using these blocks to write stream data and other data, so we mark them as the free page map now. We don't yet serialize these pages to the disk, but at least we make a note of what it is, and avoid writing random data to them. Doing this also necessitated cleaning up some of the tests to be more general and hardcode fewer values, which is nice. llvm-svn: 275629
* [pdb] Round trip the NameMap data structure to YAML.Zachary Turner2016-07-1511-8/+121
| | | | llvm-svn: 275628
* [pdb] Use MsfBuilder to handle the writing PDBs.Zachary Turner2016-07-1526-238/+344
| | | | | | | | | | | | | | | Previously we would read a PDB, then write some of it back out, but write the directory, super block, and other pertinent metadata back out unchanged. This generates incorrect PDBs since the amount of data written was not always the same as the amount of data read. This patch changes things to use the newly introduced `MsfBuilder` class to write out a correct and accurate set of Msf metadata for the data *actually* written, which opens up the door for adding and removing type records, symbol records, and other types of data to an existing PDB. llvm-svn: 275627
* StructurizeCFG: Fix inverting constantexpr conditionsMatt Arsenault2016-07-152-8/+32
| | | | llvm-svn: 275626
* [Hexagon] Handle instruction latency for 0 or 2 cyclesKrzysztof Parzyszek2016-07-155-0/+227
| | | | | | | | | | | | | | | | | | | | | | | The Hexagon schedulers need to handle instructions with a latency of 0 or 2 more accurately. The problem, in v60, is that a dependence between two instructions with a 2 cycle latency can use a .cur version of the source to achieve a 0 cycle latency when the use is in the same packet. Any othe use, must be at least 2 packets later, or a stall occurs. In other words, the compiler does not want to schedule the dependent instructions 1 cycle later. To achieve this, the latency adjustment code allows only a single dependence to have a zero latency. All other instructions have the other value, which is typically 2 cycles. We use a heuristic to determine which instruction gets the 0 latency. The Hexagon machine scheduler was also changed to increase the cost associated with 0 latency dependences than can be scheduled in the same packet. Patch by Brendon Cahoon. llvm-svn: 275625
* AMDGPU: Remove brev intrinsicMatt Arsenault2016-07-153-16/+0
| | | | llvm-svn: 275620
* AMDGPU: Fix TargetPrefix for remaining r600 intrinsicsMatt Arsenault2016-07-1539-144/+146
| | | | llvm-svn: 275619
* AMDGPU: Remove AMDGPU.ldexpMatt Arsenault2016-07-153-32/+0
| | | | llvm-svn: 275618
* AMDGPU: Remove legacy rsq.clamped intrinsicMatt Arsenault2016-07-1512-115/+70
| | | | | | | | Mesa still has a use of llvm.AMDGPU.rsq.f64 remaining. Also fix mismatch with non-IEEE rsq selecting to IEEE rsq. llvm-svn: 275617
* AMDGPU/R600: Delete dead code.Matt Arsenault2016-07-152-58/+1
| | | | | | Dead or the same as the base implementation. llvm-svn: 275616
* DebugInfo: reorder some initializersSaleem Abdulrasool2016-07-151-2/+2
| | | | | | Fix a few initialization ordering warnings from gcc from `-Wreorder`. NFC. llvm-svn: 275615
* CodeGen: avoid emitting unnecessary CFISaleem Abdulrasool2016-07-153-8/+10
| | | | | | | | | | | | Remove unnecessary clutter in assembly output. When using SjLj EH, the CFI is not actually used for anything. Do not emit the CFI needlessly. The minor test adjustments are interesting. The prologue test was just overzealous matcching. The interesting case is the LSDA change. It was originally added to ensure that various compilations did not mangle the name (it explicitly checked the name!). However, subsequent cleanups made it more reliant on the CFI to find the name. Parse the generated code flow to generically find the label still. llvm-svn: 275614
* Make processInstruction from LCSSA.cpp externally available.Michael Zolotukhin2016-07-152-120/+140
| | | | | | | | | | | | | | | | Summary: When a pass tries to keep LCSSA form it's often convenient to be able to update LCSSA for a set of instructions rather than for the entire loop. This patch makes the processInstruction from LCSSA externally available under a name formLCSSAForInstruction. Reviewers: chandlerc, sanjoy, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22378 llvm-svn: 275613
* [pdb] Introduce MsfBuilder for laying out PDB files.Zachary Turner2016-07-159-17/+854
| | | | | | | Reviewed by: ruiu Differential Revision: https://reviews.llvm.org/D22308 llvm-svn: 275611
* Teach fast isel about the win64 calling convention.Nico Weber2016-07-153-8/+10
| | | | | | | | | | | | | | | This mostly just works. Vectorcall rets are still not supported. The win64_eh test change is because fast isel doesn't use rsi for temporary computations, so it doesn't need to be pushed. The test case I'm changing was originally added to test pushes, but by now there are other test cases in that file exercising that code path. https://reviews.llvm.org/D22422 llvm-svn: 275607
* [Hexagon] Make MI scheduler check for stalls in previous packet on v60Krzysztof Parzyszek2016-07-152-3/+41
| | | | | | Patch by Ikhlas Ajbar. llvm-svn: 275606
* [CFLAA] Add attributes handling for CFLAnders.George Burgess IV2016-07-153-9/+282
| | | | | | | | | | | | This patch adds proper handling of stratified attributes into our anders-style CFLAA implementation. It also comes bundled with more CFLAnders tests. :) Patch by Jia Chen. Differential Revision: https://reviews.llvm.org/D22325 llvm-svn: 275604
* [PowerPC] Set kill flag for scratch register when spilling the link registerNemanja Ivanovic2016-07-151-1/+1
| | | | | | This fixes PR 28526. llvm-svn: 275603
* [CFLAA] Add an initial CFLAnders implementation.George Burgess IV2016-07-158-37/+629
| | | | | | | | | | | | | This adds an incomplete anders-style implementation for CFLAA. It's incomplete in that it's missing interprocedural analysis, attrs handling, etc. and that it needs more tests. More tests and features will be added in future commits. Patch by Jia Chen. Differential Revision: https://reviews.llvm.org/D22291 llvm-svn: 275602
* Fix calls to SelectionDAG::getStoreDerek Schuff2016-07-151-2/+2
| | | | | | It was refactored in r275592. NFC llvm-svn: 275601
* Revert "[AMDGPU] Add metadata for runtime"Vitaly Buka2016-07-154-1219/+0
| | | | | | This reverts commit r275566. llvm-svn: 275599
* [Hexagon] Replace postprocessDAG with a more elaborate DAG mutationKrzysztof Parzyszek2016-07-151-10/+76
| | | | llvm-svn: 275598
* [ReassociateGEP] Update tests to allow missing "inbounds" on certain GEPs.Jingyue Wu2016-07-152-9/+9
| | | | | | | | With r275532 fixing miscompilation of GVN, "inbounds" on certain GEPs in these tests cannot be preserved any more. Left a TODO in the tests for future reference. llvm-svn: 275596
* [MBP] Clean up of the comments, and a first attempt to better describe a partSjoerd Meijer2016-07-151-28/+49
| | | | | | | | of the algorithm. Differential Revision: https://reviews.llvm.org/D22364 llvm-svn: 275595
* add tests for associative ops blocked by a castSanjay Patel2016-07-151-0/+82
| | | | | | | These are more generalized versions of the cases added in r275302 and r275297. llvm-svn: 275594
* [SCCP] Merge two conditions into one. NFCI.Davide Italiano2016-07-151-3/+1
| | | | llvm-svn: 275593
* [SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, ↵Justin Lebar2016-07-1533-1659/+1217
| | | | | | | | | | | | | | | | | | | | | | | getStore, and friends. Summary: Instead, we take a single flags arg (a bitset). Also add a default 0 alignment, and change the order of arguments so the alignment comes before the flags. This greatly simplifies many callsites, and fixes a bug in AMDGPUISelLowering, wherein the order of the args to getLoad was inverted. It also greatly simplifies the process of adding another flag to getLoad. Reviewers: chandlerc, tstellarAMD Subscribers: jholewinski, arsenm, jyknight, dsanders, nemanjai, llvm-commits Differential Revision: http://reviews.llvm.org/D22249 llvm-svn: 275592
* [CodeGen] Take a MachineMemOperand::Flags in ↵Justin Lebar2016-07-1519-48/+45
| | | | | | | | | | | | | | | | | MachineFunction::getMachineMemOperand. Summary: Previously we took an unsigned. Hooray for type-safety. Reviewers: chandlerc Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D22282 llvm-svn: 275591
* [PGO] IRPGO pre-cleanup pass changesRong Xu2016-07-152-0/+44
| | | | | | | | | | | | | | This patch adds a selected set of cleanup passes including a pre-inline pass before LLVM IR PGO instrumentation. The inline is only intended to apply those obvious/trivial ones before instrumentation so that much less instrumentation is needed to get better profiling information. This will drastically improve the instrumented code performance for large C++ applications. Another benefit is the context sensitive counts that can potentially improve the PGO optimization. Differential Revision: http://reviews.llvm.org/D21405 llvm-svn: 275588
* fix documentation comments; NFCSanjay Patel2016-07-151-71/+37
| | | | llvm-svn: 275587
* [Hexagon] Add a scheduling DAG mutationKrzysztof Parzyszek2016-07-154-1/+68
| | | | | | | - Remove output dependencies on USR_OVF register. - Update chain edge latencies between v60 vector loads/stores. llvm-svn: 275586
* [OptRemark,LDist] RFC: Add hotness attributeAdam Nemet2016-07-1515-9/+337
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is the first set of changes implementing the RFC from http://thread.gmane.org/gmane.comp.compilers.llvm.devel/98334 This is a cross-sectional patch; rather than implementing the hotness attribute for all optimization remarks and all passes in a patch set, it implements it for the 'missed-optimization' remark for Loop Distribution. My goal is to shake out the design issues before scaling it up to other types and passes. Hotness is computed as an integer as the multiplication of the block frequency with the function entry count. It's only printed in opt currently since clang prints the diagnostic fields directly. E.g.: remark: /tmp/t.c:3:3: loop not distributed: use -Rpass-analysis=loop-distribute for more info (hotness: 300) A new API added is similar to emitOptimizationRemarkMissed. The difference is that it additionally takes a code region that the diagnostic corresponds to. From this, hotness is computed using BFI. The new API is exposed via an analysis pass so that it can be made dependent on LazyBFI. (Thanks to Hal for the analysis pass idea.) This feature can all be enabled by setDiagnosticHotnessRequested in the LLVM context. If this is off, LazyBFI is not calculated (D22141) so there should be no overhead. A new command-line option is added to turn this on in opt. My plan is to switch all user of emitOptimizationRemark* to use this module instead. Reviewers: hfinkel Subscribers: rcox2, mzolotukhin, llvm-commits Differential Revision: http://reviews.llvm.org/D21771 llvm-svn: 275583
* [libFuzzer] add ThreadedLeakTestKostya Serebryany2016-07-153-0/+24
| | | | llvm-svn: 275582
* [AliasAnalysis] Give back AA results for fence instructionsDavid Majnemer2016-07-153-5/+27
| | | | | | | | | | | | | Calling getModRefInfo with a fence resulted in crashes because fences don't have a memory location. Add a new predicate to Instruction called isFenceLike which indicates that the instruction mutates memory but not any single memory location in particular. In practice, it is a proxy for the set of instructions which "mayWriteToMemory" but cannot be used with MemoryLocation::get. This fixes PR28570. llvm-svn: 275581
* [Hexagon] Update instruction itinerariesKrzysztof Parzyszek2016-07-157-120/+128
| | | | llvm-svn: 275578
* [PM] Convert LoopInstSimplify Pass to new PMDehao Chen2016-07-156-62/+121
| | | | | | | | | | | | Summary: Convert LoopInstSimplify to new PM. Unfortunately there is no exisiting unittest for this pass. Reviewers: davidxl, silvas Subscribers: silvas, llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D22280 llvm-svn: 275576
* IR: Sort generic intrinsics before target specific onesJustin Bogner2016-07-156-44/+111
| | | | | | | | | | | | This splits out the intrinsic table such that generic intrinsics come first and target specific intrinsics are grouped by target. From here we can find out which target an intrinsic is for or differentiate between generic and target intrinsics. The motivation here is to make it easier to move target specific intrinsic handling out of generic code. llvm-svn: 275575
* [Hexagon] Fixes/changes to instruction selectionKrzysztof Parzyszek2016-07-152-27/+72
| | | | | | | | - Add patterns for rr/abs addressing modes. - Set addrMode to PostInc where necessary. - Misc fixes. llvm-svn: 275574
* [DSE]Enhance shorthening MemIntrinsic based on OverlapIntervalsJun Bum Lim2016-07-153-50/+169
| | | | | | | | | | | | | | Summary: This change use the overlap interval map built from partial overwrite tracking to perform shortening MemIntrinsics. Add test cases which was missing opportunities before. Reviewers: hfinkel, eeckstein, mcrosier Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D21909 llvm-svn: 275571
* [Hexagon] Improve patterns with stack-based addressingKrzysztof Parzyszek2016-07-158-353/+683
| | | | | | | | | - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
* In dag-optnone.ll, use varargs instead of win64 to fast SDIsel.Nico Weber2016-07-151-8/+7
| | | | | | | | The test used to rely on targeting win64 to disable fast isel, but I'd like to teach fast isel about win64 rets. Change the test to use varargs to disable fast isel. llvm-svn: 275568
* [LV] Swap A and B in interleaved access analysis (NFC)Matthew Simpson2016-07-151-77/+87
| | | | | | | | | This patch swaps A and B in the interleaved access analysis and clarifies related comments. The algorithm is more intuitive if we let access A precede access B in program order rather than the reverse. This change was requested in the review of D19984. llvm-svn: 275567
* [AMDGPU] Add metadata for runtimeYaxun Liu2016-07-154-0/+1219
| | | | | | | | | | Added emitting metadata to elf for runtime. Runtime requires certain information (metadata) about kernels to be able to execute and query them. Such information is emitted to an elf section as a key-value pair stream. Differential Revision: https://reviews.llvm.org/D21849 llvm-svn: 275566
* Rename AnalyzeBranch* to analyzeBranch*.Jacques Pienaar2016-07-1554-133/+134
| | | | | | | | | | | | Summary: NFC. Rename AnalyzeBranch/AnalyzeBranchPredicate to analyzeBranch/analyzeBranchPredicate to follow LLVM coding style and be consistent with TargetInstrInfo's analyzeCompare and analyzeSelect. Reviewers: tstellarAMD, mcrosier Subscribers: mcrosier, jholewinski, jfb, arsenm, dschuff, jyknight, dsanders, nemanjai Differential Revision: https://reviews.llvm.org/D22409 llvm-svn: 275564
* Re-submit r272891 "Prevent dangling pointer problems in BranchProbabilityInfo"Igor Laevsky2016-07-152-0/+30
| | | | | | | | | Most possibly problem was caused by the same reason as PR28400. This change bypasses it by using CallbackVH instead of AssertingVH. Differential Revision: https://reviews.llvm.org/D20957 llvm-svn: 275563
* Revert r275141 - Mips: Avoid implicit iterator conversions, NFCDaniel Sanders2016-07-156-51/+57
| | | | | | It appears to have caused some failures in our buildbots. llvm-svn: 275562
* code hoisting pass based on GVNSebastian Pop2016-07-1512-4/+1646
| | | | | | | | | | | | | This pass hoists duplicated computations in the program. The primary goal of gvn-hoist is to reduce the size of functions before inline heuristics to reduce the total cost of function inlining. Pass written by Sebastian Pop, Aditya Kumar, Xiaoyu Hu, and Brian Rzycki. Important algorithmic contributions by Daniel Berlin under the form of reviews. Differential Revision: http://reviews.llvm.org/D19338 llvm-svn: 275561
* [LLVM][MIPS] Fix createStubFunction to emit JR encoding based on Arch.Nitesh Jain2016-07-152-2/+9
| | | | | | | | | | Reviewers: vkalintiris, dsanders Subscribers: jaydeep, bhushan, mohit.bhakkad, slthakur, llvm-commits Differential Revision: https://reviews.llvm.org/D21172 llvm-svn: 275559
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