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* ARM: fix vmov.i64 immediate validity checkTim Northover2016-07-142-1/+4
| | | | | | Typo meant we were only checking the low byte (repeatedly). llvm-svn: 275437
* GlobalsAA: Functions with the argmemonly attribute won't read arbitrary globalsTom Stellard2016-07-142-1/+32
| | | | | | | | | | | | | | | | | Summary: In preparation for changing GlobalsAA to stop assuming that intrinsics can't read arbitrary globals, we need to make sure GlobalsAA is querying function attributes rather than relying on this assumption. This patch was inspired by: http://reviews.llvm.org/D20206 Reviewers: jmolloy, hfinkel Subscribers: eli.friedman, llvm-commits Differential Revision: https://reviews.llvm.org/D21318 llvm-svn: 275433
* Don't optimize movs to pushes in -O0 builds.Nico Weber2016-07-143-24/+24
| | | | | | https://reviews.llvm.org/D22362 llvm-svn: 275431
* Delete some trailing whitespace.Nico Weber2016-07-141-2/+2
| | | | llvm-svn: 275429
* [X86] Decode MPX BND registers.Ahmed Bougacha2016-07-143-15/+29
| | | | | | | | | | | | | We were able to assemble, but not disassemble. Note that fixupRMValue was truncating EA_REG_BND0-3 because we hit the uint8_t max. The control registers were already squarely above it, but I don't think they ever go in .r/m, only in .reg. I also did notice an extra REX.W in our encoding, but I think that's fine. llvm-svn: 275427
* [X86] Don't mark addressing mode operands as "outs". NFC-ish.Ahmed Bougacha2016-07-141-12/+12
| | | | | | | Nothing in-tree can tell the difference, but it's incorrect: the addressing mode registers aren't what's defined. llvm-svn: 275426
* [TableGen] Autobrief-ize Record. NFC.Ahmed Bougacha2016-07-142-75/+75
| | | | llvm-svn: 275425
* [TableGen] Cleanup Record comments. NFC.Ahmed Bougacha2016-07-142-68/+4
| | | | | | | LLVM doesn't use exceptions anymore. Also remove the implementation comments. Some of them diverged. llvm-svn: 275424
* [GlobalISel] Fix #include ordering/spacing. NFC.Ahmed Bougacha2016-07-142-3/+2
| | | | llvm-svn: 275423
* [AMDGPU] Assembler: fix row_bcast parsingSam Kolton2016-07-142-0/+14
| | | | | | | | | | | | Summary: This change fix bug 28538 Reviewers: tstellarAMD, vpykhtin Subscribers: arsenm, kzhuravl Differential Revision: https://reviews.llvm.org/D22355 llvm-svn: 275422
* Revert r275411, it cause PR28552.Nico Weber2016-07-146-19/+18
| | | | llvm-svn: 275421
* Revert r275401, it caused PR28551.Nico Weber2016-07-1412-1643/+4
| | | | llvm-svn: 275420
* [LV] Avoid unnecessary IV scalar-to-vector-to-scalar conversionsMatthew Simpson2016-07-143-69/+118
| | | | | | | | | | | | This patch prevents increases in the number of instructions, pre-instcombine, due to induction variable scalarization. An increase in instructions can lead to an increase in the compile-time required to simplify the induction variables. We now maintain a new map for scalarized induction variables to prevent us from converting between the scalar and vector forms. This patch should resolve compile-time regressions seen after r274627. llvm-svn: 275419
* Teach fast isel calls and rets about stdcall.Nico Weber2016-07-143-6/+31
| | | | | | | stdcall is callee-pop like thiscall, so the thiscall changes already did most of the work for this. This change only opts stdcall in and adds tests. llvm-svn: 275414
* [X86][AVX] Added an additional vperm2f128 memory folding testSimon Pilgrim2016-07-141-0/+12
| | | | llvm-svn: 275413
* Remove trailing whitespace.Simon Pilgrim2016-07-141-1/+1
| | | | llvm-svn: 275412
* [X86][AVX2] Allow VPERMPD/VPERMQ shuffles to call combineShuffleSimon Pilgrim2016-07-146-18/+19
| | | | | | This improves the situation discussed in D19228 where we were forcing VPERMPD/VPERMQ where VPERM2F128/VPERM2I128 would have been better. llvm-svn: 275411
* [mips] SelectionDAGISel subclasses now follow the optimization level.Daniel Sanders2016-07-147-13/+40
| | | | | | | | | | | | | | | | Summary: It was recently discovered that, for Mips's SelectionDAGISel subclasses, all optimization levels caused SelectionDAGISel to behave like -O2. This change adds the necessary plumbing to initialize the optimization level. Reviewers: andrew.w.kaylor Subscribers: andrew.w.kaylor, sdardis, dean, llvm-commits, vradosavljevic, petarj, qcolombet, probinson, dsanders Differential Revision: https://reviews.llvm.org/D14900 llvm-svn: 275410
* Upgrade all the .arcconfigs to https.Benjamin Kramer2016-07-141-1/+1
| | | | llvm-svn: 275409
* Speculatively fix the sphinx build, which does not think the original code ↵Aaron Ballman2016-07-141-4/+4
| | | | | | was valid nasm (http://lab.llvm.org:8011/builders/llvm-sphinx-docs/builds/11854/steps/docs-llvm-html/logs/stdio). llvm-svn: 275408
* [X86][AVX] Add support for narrowing 128-bit+ shuffle mask elements to ↵Simon Pilgrim2016-07-143-35/+32
| | | | | | | | 64-bits to allow combining Primarily this is to allow blend with zero instead of having to use vperm2f128, but we can use this in the future to deal with AVX512 cases where we need to keep the original element size to correctly fold masked operations. llvm-svn: 275406
* This converts a signed remainder instruction to unsigned remainder, whichSjoerd Meijer2016-07-142-15/+59
| | | | | | | | | | enables the code size optimisation to fold a rem and div into a single aeabi_uidivmod call. This was not happening before because sdiv was converted but srem not, and instructions with different signedness are not combined. Differential Revision: http://reviews.llvm.org/D22214 llvm-svn: 275403
* [X86][AVX] Add 128-bit wide shuffle tests that should combine to blend-with-zeroSimon Pilgrim2016-07-142-0/+38
| | | | llvm-svn: 275402
* code hoisting pass based on GVNSebastian Pop2016-07-1412-4/+1643
| | | | | | | | | | | | | This pass hoists duplicated computations in the program. The primary goal of gvn-hoist is to reduce the size of functions before inline heuristics to reduce the total cost of function inlining. Pass written by Sebastian Pop, Aditya Kumar, Xiaoyu Hu, and Brian Rzycki. Important algorithmic contributions by Daniel Berlin under the form of reviews. Differential Revision: http://reviews.llvm.org/D19338 llvm-svn: 275401
* [X86][AVX] Add VBROADCASTF128/VBROADCASTI128 shuffle comments supportSimon Pilgrim2016-07-145-8/+31
| | | | llvm-svn: 275400
* Remove extra ';' to appease -WpedanticDean Michael Berris2016-07-141-1/+1
| | | | | | | | | Summary: Reviewers: dok Subscribers: llvm-commits llvm-svn: 275399
* [X86][AVX] Regenerate broadcast upgrade testsSimon Pilgrim2016-07-142-17/+24
| | | | llvm-svn: 275398
* [X86][AVX2] VBROADCASTSSrr/VBROADCASTSSYrr require AVX2 not AVXSimon Pilgrim2016-07-141-1/+1
| | | | llvm-svn: 275391
* This implements a more optimal algorithm for selecting a base constant inSjoerd Meijer2016-07-148-7/+186
| | | | | | | | | | | | | | constant hoisting. It not only takes into account the number of uses and the cost of expressions in which constants appear, but now also the resulting integer range of the offsets. Thus, the algorithm maximizes the number of uses within an integer range that will enable more efficient code generation. On ARM, for example, this will enable code size optimisations because less negative offsets will be created. Negative offsets/immediates are not supported by Thumb1 thus preventing more compact instruction encoding. Differential Revision: http://reviews.llvm.org/D21183 llvm-svn: 275382
* [InstCombine] Masked loads with undef masks can fold to normal loadsDavid Majnemer2016-07-142-6/+28
| | | | | | | | We were able to fold masked loads with an all-ones mask to a normal load. However, we couldn't turn a masked load with a mask with mixed ones and undefs into a normal load. llvm-svn: 275380
* Simplify llvm.masked.load w/ undef masksDavid Majnemer2016-07-143-19/+49
| | | | | | | We can always pick the passthru value if the mask is undef: we are permitted to treat the mask as-if it were filled with zeros. llvm-svn: 275379
* [AVX512] Implement EXTLOAD lowering with patterns to select existing VPMOVZX ↵Craig Topper2016-07-141-46/+76
| | | | | | instructions instead of creating CodeGenOnly instructions. llvm-svn: 275378
* [X86] Fix stupid typo in isel lowering.Eli Friedman2016-07-142-1/+37
| | | | | | | Apparently someone miscounted the number of zeros in the immediate. Fixes https://llvm.org/bugs/show_bug.cgi?id=28544 . llvm-svn: 275376
* AMDGPU/R600: Delete/rename intrinsics no longer used by mesaMatt Arsenault2016-07-1424-1721/+1450
| | | | | | Use the replacement pass to update the tests, and delete old names. llvm-svn: 275375
* AMDGPU/R600: Remove intrinsics with no tests and no usersMatt Arsenault2016-07-144-76/+15
| | | | | | Mesa removed this path, so nothing is using these anymore. llvm-svn: 275372
* AMDGPU: Remove unused intrinsicsMatt Arsenault2016-07-143-119/+0
| | | | llvm-svn: 275371
* AMDGPU: Fix test not actually testing anythingMatt Arsenault2016-07-142-4/+28
| | | | | | | | | | It wasn't actually running the pass, and since it is missing the llvm prefix, the eh intrinsic was not really an IntrinsicInst. Also add missing test for lifetime markers. llvm-svn: 275370
* AMDGPU: Remove dead codeMatt Arsenault2016-07-142-10/+0
| | | | llvm-svn: 275369
* XRay: Add entry and exit sledsDean Michael Berris2016-07-1418-12/+317
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: In this patch we implement the following parts of XRay: - Supporting a function attribute named 'function-instrument' which currently only supports 'xray-always'. We should be able to use this attribute for other instrumentation approaches. - Supporting a function attribute named 'xray-instruction-threshold' used to determine whether a function is instrumented with a minimum number of instructions (IR instruction counts). - X86-specific nop sleds as described in the white paper. - A machine function pass that adds the different instrumentation marker instructions at a very late stage. - A way of identifying which return opcode is considered "normal" for each architecture. There are some caveats here: 1) We don't handle PATCHABLE_RET in platforms other than x86_64 yet -- this means if IR used PATCHABLE_RET directly instead of a normal ret, instruction lowering for that platform might do the wrong thing. We think this should be handled at instruction selection time to by default be unpacked for platforms where XRay is not availble yet. 2) The generated section for X86 is different from what is described from the white paper for the sole reason that LLVM allows us to do this neatly. We're taking the opportunity to deviate from the white paper from this perspective to allow us to get richer information from the runtime library. Reviewers: sanjoy, eugenis, kcc, pcc, echristo, rnk Subscribers: niravd, majnemer, atrick, rnk, emaste, bmakam, mcrosier, mehdi_amini, llvm-commits Differential Revision: http://reviews.llvm.org/D19904 llvm-svn: 275367
* [SCCP] Pass a Value * instead of templating this function. NFC.Davide Italiano2016-07-141-9/+8
| | | | | | Thanks to Eli for the suggestion! llvm-svn: 275366
* clarify a bit.Chris Lattner2016-07-141-1/+1
| | | | llvm-svn: 275364
* [IPSCCP] Constant fold struct argument/instructions when all the lattice ↵Davide Italiano2016-07-142-13/+15
| | | | | | | | | | | values are constant. This now should also work with the interprocedural variant of the pass. Slightly easier now that the yak is shaved. Differential Revision: http://reviews.llvm.org/D22329 llvm-svn: 275363
* [Object] Re-apply r275316 now that I have the corresponding LLD patch ready.Lang Hames2016-07-1415-197/+236
| | | | llvm-svn: 275361
* Teach fast isel about thiscall (and callee-pop) calls.Nico Weber2016-07-142-10/+26
| | | | | | http://reviews.llvm.org/D22315 llvm-svn: 275360
* [Scalarizer] PR28108: Skip over nullptr rather than crashing on it.Mehdi Amini2016-07-142-1/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: In Scalarizer::gather we see if we already have a scattered form of Op, and in that case use the new form. In the particular case of PR28108, the found ValueVector SV has size 2, where the first Value is nullptr, and the second is indeed a proper Value. The nullptr then caused an assert to blow when we tried to do cast<Instruction>(SV[I]). With this patch we check SV[I] before doing the cast, and if it's nullptr we just skip over it. I don't know the Scalarizer well enough to know if this is the best fix or if something should be done else where to prevent the nullptr from being in the ValueVector at all, but at least this avoids the crash and looking at the test case output it looks reasonable. Reviewers: hfinkel, frasercrmck, wala, mehdi_amini Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D21518 llvm-svn: 275359
* Add missing test for r275347 "[IPRA] Set callee saved registers to none for ↵Mehdi Amini2016-07-141-0/+30
| | | | | | local function when IPRA is enabled." llvm-svn: 275358
* [SCCP] Generalize tryToReplaceInstWithConstant to work also with arguments.Davide Italiano2016-07-141-22/+18
| | | | llvm-svn: 275357
* MIRParser: Fix MIRParser not reporting nullptr on error.Matthias Braun2016-07-141-1/+1
| | | | | | | While some code paths in MIRParserImpl::parse() already returned nullptr in case of error one of the important ones did not. llvm-svn: 275355
* Synchronize LLVM and clang's ObjCDeclSpec::ObjCPropertyAttributeKind.Adrian Prantl2016-07-147-19/+77
| | | | | | | | | | This adds Clang-specific DWARF constants for nullability and ObjC class properties that are already generated by clang. This patch adds dwarfdump support and a more comprehensive testcase. <rdar://problem/27335745> llvm-svn: 275354
* [Object] Revert r275316, Archive::child_iterator changes, while I update lld.Lang Hames2016-07-1415-236/+197
| | | | | | Should fix the bots broken by r275316. llvm-svn: 275353
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