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* Unbreaking the non-x86 build bots by protecting the AVX test code properly.Aaron Ballman2013-05-031-0/+4
| | | | llvm-svn: 180992
* Correctly testing for AVX support in x86 based off code from Hosts.cpp.Aaron Ballman2013-05-031-1/+18
| | | | llvm-svn: 180991
* [mips] Remove "Commutative" from property list of non-commutative intrinsics.Akira Hatanaka2013-05-031-8/+8
| | | | llvm-svn: 180988
* Fix missing include in Hexagon code for Release+AssertsReid Kleckner2013-05-031-0/+1
| | | | llvm-svn: 180983
* In MC asm parsing, account for the possibility of whitespace withinJohn McCall2013-05-032-19/+24
| | | | | | | | | | | | | | the "identifier" parsed by the frontend callback by skipping forward until we've consumed a token that ends at the point dictated by the callback. In addition, inform the callback when it's parsing an unevaluated operand (e.g. mov eax, LENGTH A::x) as opposed to an evaluated one (e.g. mov eax, [A::x]). This commit depends on a clang commit. llvm-svn: 180978
* [mips] Handle reading, writing or copying of ccond field of DSP controlAkira Hatanaka2013-05-024-1/+80
| | | | | | | | | | | | register. - Define pseudo instructions which store or load ccond field of the DSP control register. - Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack. - Expand the pseudos before callee-scan save. - Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs. llvm-svn: 180969
* Remove redundant flag.Bill Wendling2013-05-021-1/+1
| | | | llvm-svn: 180967
* reverting r180953Jyotsna Verma2013-05-025-305/+404
| | | | llvm-svn: 180964
* R600: Signed literals are 64bits wideVincent Lejeune2013-05-022-3/+168
| | | | llvm-svn: 180960
* R600: If previous bundle is dot4, PV valid chan is always XVincent Lejeune2013-05-022-38/+295
| | | | llvm-svn: 180959
* R600: Add a test to check that use_kill is emittedVincent Lejeune2013-05-021-0/+1
| | | | llvm-svn: 180958
* R600: Improve asmPrint of ALU clauseVincent Lejeune2013-05-023-4/+20
| | | | llvm-svn: 180957
* R600: Prettier asmPrint of AluVincent Lejeune2013-05-0238-114/+172
| | | | llvm-svn: 180956
* Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.Jyotsna Verma2013-05-025-404/+305
| | | | llvm-svn: 180953
* [GV] Remove dead code which is really difficult to decipher.Shuxin Yang2013-05-021-26/+2
| | | | | | | | | | | Actually it took me couple of hours trying to make sense of them and only to find they are dead code. I guess the original author used "allSingleSucc" to indicate if there are any critial edge emanating from some blocks, and tried to perform code motion (actually speculation) in the presence of these critical edges; but later on he/she changed mind and decided to perform edge-splitting first. llvm-svn: 180951
* We don't want FP elimination when doing an Apple-style build.Bill Wendling2013-05-022-2/+2
| | | | llvm-svn: 180949
* Replaced usages of size_type with size_t to be more consistent.Aaron Ballman2013-05-021-8/+8
| | | | llvm-svn: 180947
* Hexagon - Add peephole optimizations for zero extends.Pranav Bhandarkar2013-05-024-6/+64
| | | | | | | | | | | | * lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a sequence of a pair of i32->i64 extensions followed by a "bitwise or" into COMBINE_rr. * lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg. * test/CodeGen/Hexagon/union-1.ll: New test. * test/CodeGen/Hexagon/combine_ir.ll: Fix test. llvm-svn: 180946
* [mips] Fix the head Mips16RegisterInfo.cpp commentRichard Sandiford2013-05-021-2/+1
| | | | | | ...aka a test commit. llvm-svn: 180936
* TBAA: remove !tbaa from testing cases if not used.Manman Ren2013-05-029-182/+138
| | | | | | | This will make it easier to turn on struct-path aware TBAA since the metadata format will change. llvm-svn: 180935
* Provide an API to temporarily suppress DebugLocations from being attachedAdrian Prantl2013-05-021-0/+21
| | | | | | | | | to emitted instructions. Use this if you want an instruction to be counted towards the prologue or if there is no useful source location. rdar://problem/13442648 llvm-svn: 180929
* Hexagon: Honor __builtin_expect by using branch probabilities.Jyotsna Verma2013-05-024-37/+122
| | | | | | | | | | | | | * lib/Target/Hexagon/HexagonInstrInfo.cpp (GetDotNewPredOp): Given a jump opcode return the right pred.new jump opcode with a taken vs not-taken hint based on branch probabilities provided by the target independent module. * lib/Target/Hexagon/HexagonVLIWPacketizer.cpp: Use the above function. * lib/Target/Hexagon/HexagonNewValueJump.cpp(getNewvalueJumpOpcode): Enhance existing function use branch probabilities like HexagonInstrInfo::GetDotNewPredOp but for New Value (GPR) Jumps. llvm-svn: 180923
* R600: Use new tablegen syntax for patternsTom Stellard2013-05-023-447/+381
| | | | | | | | All but two patterns have been converted to the new syntax. The remaining two patterns will require COPY_TO_REGCLASS instructions, which the VLIW DAG Scheduler cannot handle. llvm-svn: 180922
* R600/SI: remove nonsense select patternTom Stellard2013-05-021-8/+1
| | | | | | | | Fortunately this pattern never matched, otherwise we would have generated incorrect code. Signed-off-by: Christian K??nig <christian.koenig@amd.com> llvm-svn: 180921
* Added table of contents declaration in CommandLine Library documentation.Tobias Grosser2013-05-021-0/+3
| | | | | Contributed-by: Dan Liew <daniel.liew@imperial.ac.uk> llvm-svn: 180919
* 80-col fixup.Michael Liao2013-05-021-2/+3
| | | | llvm-svn: 180915
* Avoid duplicating logic on frame register selecting when lowering eh_returnMichael Liao2013-05-021-9/+11
| | | | | | No functionality change llvm-svn: 180914
* Avoid duplicating logic on frame register selecting when lowering frameaddrMichael Liao2013-05-021-1/+3
| | | | | | No functionality change llvm-svn: 180912
* Rewrite X86 codegen regression test with FileCheckMichael Liao2013-05-021-4/+7
| | | | llvm-svn: 180910
* Add a test for the foldSelectICmpAndOr fix committed in r180779.David Majnemer2013-05-021-0/+13
| | | | | | | This tests a case where C1 and C2 were the same but X and Y were different widths. llvm-svn: 180907
* TiedTo flag can now be placed on implicit operands. isTwoAddrUse() should lookEvan Cheng2013-05-021-5/+3
| | | | | | | | | | | at all of the operands. Previously it was skipping over implicit operands which cause infinite looping when the two-address pass try to reschedule a two-address instruction below the kill of tied operand. I'm unable to come up with a reasonably sized test case. rdar://13747577 llvm-svn: 180906
* [mips] Rename class and functions. Simplify code.Akira Hatanaka2013-05-011-26/+29
| | | | | | No functionality changes. llvm-svn: 180897
* This exposes more MCJIT options via the C API:Filip Pizlo2013-05-016-44/+85
| | | | | | | | | | | | | | | | | | | | | CodeModel: It's now possible to create an MCJIT instance with any CodeModel you like. Previously it was only possible to create an MCJIT that used CodeModel::JITDefault. EnableFastISel: It's now possible to turn on the fast instruction selector. The CodeModel option required some trickery. The problem is that previously, we were ensuring future binary compatibility in the MCJITCompilerOptions by mandating that the user bzero's the options struct and passes the sizeof() that he saw; the bindings then bzero the remaining bits. This works great but assumes that the bitwise zero equivalent of any field is a sensible default value. But this is not the case for LLVMCodeModel, or its internal equivalent, llvm::CodeModel::Model. In both of those, the default for a JIT is CodeModel::JITDefault (or LLVMCodeModelJITDefault), which is not bitwise zero. Hence this change introduces LLVMInitializeMCJITCompilerOptions(), which will initialize the user's options struct with defaults. The user will use this in the same way that they would have previously used memset() or bzero(). MCJITCAPITest.cpp illustrates the change, as does the comment in ExecutionEngine.h. llvm-svn: 180893
* Avoid generating tempfile(s) never usedMichael Liao2013-05-011-2/+2
| | | | | | As DejaGNU is deprecated, it seems pipe-jam issue doesn't exist any more. llvm-svn: 180892
* Rename 'struct LLVMTargetMachine' to 'struct LLVMOpaqueTargetMachine'. Filip Pizlo2013-05-011-1/+1
| | | | | | This avoids namespace collisions with llvm::LLVMTargetMachine. llvm-svn: 180891
* Revert r180737. The companion patch was reverted, and this is not relevant ↵Bill Wendling2013-05-013-105/+0
| | | | | | right now. llvm-svn: 180889
* Hexagon: Use multiclass for Jump instructions.Jyotsna Verma2013-05-0114-263/+336
| | | | llvm-svn: 180885
* Hexagon: Clear isKill flag on the predicate register inJyotsna Verma2013-05-011-1/+5
| | | | | | PredicateInstruction function. llvm-svn: 180884
* Add support for other typeinfo encodings in the ExceptionDemo.Rafael Espindola2013-05-011-9/+41
| | | | | | | | The old jit always uses DW_EH_PE_absptr, but MCJIT can use other encodings. This is in preparation for adding EH support to MCJIT, but not directly related, so I am committing it first. llvm-svn: 180883
* Fix file header comment.Filip Pizlo2013-05-011-1/+1
| | | | llvm-svn: 180882
* This patch breaks up Wrap.h so that it does not have to include all of Filip Pizlo2013-05-0132-145/+156
| | | | | | | | | | | | | | | | | | | | | | | | the things, and renames it to CBindingWrapping.h. I also moved CBindingWrapping.h into Support/. This new file just contains the macros for defining different wrap/unwrap methods. The calls to those macros, as well as any custom wrap/unwrap definitions (like for array of Values for example), are put into corresponding C++ headers. Doing this required some #include surgery, since some .cpp files relied on the fact that including Wrap.h implicitly caused the inclusion of a bunch of other things. This also now means that the C++ headers will include their corresponding C API headers; for example Value.h must include llvm-c/Core.h. I think this is harmless, since the C API headers contain just external function declarations and some C types, so I don't believe there should be any nasty dependency issues here. llvm-svn: 180881
* SROA: Generate selects instead of shuffles when blending values because this ↵Nadav Rotem2013-05-012-22/+20
| | | | | | | | is the cannonical form. Shuffles are more difficult to lower and we usually don't touch them, while we do optimize selects more often. llvm-svn: 180875
* [inline asm] Return an undef SDValue of the expected value type, rather thanChad Rosier2013-05-011-1/+1
| | | | | | | | | report a fatal error. This allows us to continue processing the translation unit. Test case to come on the clang side because we need an inline asm diagnostics handler in place. rdar://13446483 llvm-svn: 180873
* Optimize away nop CONCAT_VECTOR nodes.Nadav Rotem2013-05-012-0/+52
| | | | | | | | | Optimize CONCAT_VECTOR nodes that merge EXTRACT_SUBVECTOR values that extract from the same vector. rdar://13402653 PR15866 llvm-svn: 180871
* Updating the getting started guide for Visual Studio users. Specifically, ↵Aaron Ballman2013-05-011-3/+6
| | | | | | pointing out that you have to pass additional parameters to llvm-lit and explicitly specify python on the command line. llvm-svn: 180869
* get rid of windows warning:Peng Cheng2013-05-011-1/+2
| | | | | | warning C4946: reinterpret_cast used between related classes llvm-svn: 180852
* get rid of windows warning:Peng Cheng2013-05-011-1/+1
| | | | | | warning C4800: forcing value to bool 'true' or 'false' (performance warning) llvm-svn: 180851
* replace reinterpret_cast by cast or remove reinterpret_cast to get rid of ↵Peng Cheng2013-05-011-9/+10
| | | | | | windows warning: warning C4946: reinterpret_cast used between related classes. llvm-svn: 180850
* fix windows warning. Peng Cheng2013-05-011-2/+2
| | | | | | warning C4244: 'argument' : conversion from 'uint64_t' to 'const unsigned int', possible loss of data llvm-svn: 180847
* use static_cast to get rid of windows warning. Peng Cheng2013-05-011-1/+1
| | | | | | warning C4244: 'argument' : conversion from 'uint64_t' to 'const unsigned int', possible loss of data llvm-svn: 180846
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