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* Hoist the insertVector helper to be a static helper.Chandler Carruth2012-12-171-49/+62
| | | | | | | | | | | | | | | This will allow its use inside of memcpy rewriting as well. This routine is more complex than extractVector, and some of its uses are not 100% where I want them to be so there is still some work to do here. While this can technically change the output in some cases, it shouldn't be a change that matters -- IE, it can leave some dead code lying around that prior versions did not, etc. Yet another step in the refactorings leading up to the solution to the last component of PR14478. llvm-svn: 170328
* Add instruction encodings for ZEXT and SEXT.Richard Osborne2012-12-172-8/+14
| | | | | | Previously these were marked with the wrong format. llvm-svn: 170327
* Lift the extractVector helper all the way out to a static helper function.Chandler Carruth2012-12-171-30/+32
| | | | | | | | | | | | | | | | | The method helpers all implicitly act upon the alloca, and what we really want is a fully generic helper. Doing memcpy rewrites is more special than all other rewrites because we are at times rewriting instructions which touch pointers *other* than the alloca. As a consequence all of the helpers needed by memcpy rewriting of sub-vector copies will need to be generalized fully. Note that all of these helpers ({insert,extract}{Integer,Vector}) are woefully uncommented. I'm going to go back through and document them once I get the factoring correct. No functionality changed. llvm-svn: 170325
* Factor the vector load rewriting into a more generic form.Chandler Carruth2012-12-171-16/+27
| | | | | | | | | This makes it suitable for use in rewriting memcpy in the presence of subvector memcpy intrinsics. No functionality changed. llvm-svn: 170324
* Add instruction encodings / disassembly support for 2r instructions.Richard Osborne2012-12-174-70/+222
| | | | llvm-svn: 170323
* Add instruction encodings / disassembly support for 0r instructions.Richard Osborne2012-12-173-9/+32
| | | | llvm-svn: 170322
* Simplify assertion in XCoreInstPrinter.Richard Osborne2012-12-171-2/+3
| | | | llvm-svn: 170321
* Update comments to match recommended doxygen style.Richard Osborne2012-12-174-16/+17
| | | | llvm-svn: 170320
* Remove unnecessary include.Richard Osborne2012-12-171-1/+0
| | | | llvm-svn: 170319
* Fix typo that results in new landing pads not getting a name, fixing PR14617.Duncan Sands2012-12-171-1/+1
| | | | | | Patch by Chris Toshok. llvm-svn: 170318
* Fix comment typo.Duncan Sands2012-12-171-1/+1
| | | | llvm-svn: 170317
* Remove EFLAGS from the BLSI/BLSMSK/BLSR patterns. The nodes created by DAG ↵Craig Topper2012-12-171-11/+11
| | | | | | combine don't contain an EFLAGS def. llvm-svn: 170308
* Simplify BMI ANDN matching to use patterns instead of a DAG combine. Also ↵Craig Topper2012-12-174-13/+16
| | | | | | add ANDN to isDefConvertible. llvm-svn: 170305
* Add rest of BMI/BMI2 instructions to the folding tables as well as popcnt ↵Craig Topper2012-12-172-1/+102
| | | | | | and lzcnt. llvm-svn: 170304
* Remove store forms of DEC/INC from isDefConvertible. Since they are stores ↵Craig Topper2012-12-171-6/+2
| | | | | | they don't have a register def. llvm-svn: 170303
* Fix the first part of PR14478: memset now works.Chandler Carruth2012-12-172-34/+103
| | | | | | | | | | | | | | | | | | | PR14478 highlights a serious problem in SROA that simply wasn't being exercised due to a lack of vector input code mixed with C-library function calls. Part of SROA was written carefully to handle subvector accesses via memset and memcpy, but the rewriter never grew support for this. Fixing it required refactoring the subvector access code in other parts of SROA so it could be shared, and then fixing the splat formation logic and using subvector insertion (this patch). The PR isn't quite fixed yet, as memcpy is still broken in the same way. I'm starting on that series of patches now. Hopefully this will be enough to bring the bullet benchmark back to life with the bb-vectorizer enabled, but that may require fixing memcpy as well. llvm-svn: 170301
* Extract the logic for inserting a subvector into a vector alloca.Chandler Carruth2012-12-171-38/+50
| | | | | | | No functionality changed. Another step of refactoring toward solving PR14487. llvm-svn: 170300
* Lift the integer splat computation into a helper function.Chandler Carruth2012-12-171-11/+28
| | | | | | | | No functionality changed. Refactoring leading up to the fix for PR14478 which requires some significant changes to the memset and memcpy rewriting. llvm-svn: 170299
* Add debug prints for when optimizeLoadInstr folds a load.Craig Topper2012-12-171-0/+6
| | | | llvm-svn: 170298
* Add tests for disassembly of 1r XCore instructions.Richard Osborne2012-12-162-0/+45
| | | | llvm-svn: 170295
* Add instruction encodings and disassembly for 1r instructions.Richard Osborne2012-12-167-42/+113
| | | | llvm-svn: 170293
* Add XCore disassembler.Richard Osborne2012-12-167-2/+113
| | | | | | | | Currently there is no instruction encoding info and XCoreDisassembler::getInstruction() always returns Fail. I intend to add instruction encodings and tests in follow on commits. llvm-svn: 170292
* Remove invalid instruction encodings.Richard Osborne2012-12-161-18/+0
| | | | llvm-svn: 170291
* Mark anything deriving from PseudoInstXCore as a pseudo instruction.Richard Osborne2012-12-161-1/+3
| | | | llvm-svn: 170290
* Set instruction size correctly in XCoreInstrFormats.tdRichard Osborne2012-12-161-20/+21
| | | | llvm-svn: 170289
* Change XCoreAsmPrinter to lower MachineInstrs to MCInsts before emission.Richard Osborne2012-12-1614-27/+401
| | | | | | | This change adds XCoreMCInstLower to do the lowering to MCInst and XCoreInstPrinter to print the MCInsts. llvm-svn: 170288
* Replace ${:comment} with the comment symbol.Richard Osborne2012-12-161-6/+6
| | | | llvm-svn: 170286
* Declare class DwarfDebug before use instead of relying on a forward declarationDmitri Gribenko2012-12-161-0/+1
| | | | | | | | from some other unrelated header. Patch by Kai. llvm-svn: 170284
* MCPureStreamer.cpp: Try to fix build, pruning EmitDebugLabel().NAKAMURA Takumi2012-12-161-1/+0
| | | | llvm-svn: 170280
* This patch is needed to make c++ exceptions work for mips16.Reed Kotler2012-12-1617-4/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mips16 is really a processor decoding mode (ala thumb 1) and in the same program, mips16 and mips32 functions can exist and can call each other. If a jal type instruction encounters an address with the lower bit set, then the processor switches to mips16 mode (if it is not already in it). If the lower bit is not set, then it switches to mips32 mode. The linker knows which functions are mips16 and which are mips32. When relocation is performed on code labels, this lower order bit is set if the code label is a mips16 code label. In general this works just fine, however when creating exception handling tables and dwarf, there are cases where you don't want this lower order bit added in. This has been traditionally distinguished in gas assembly source by using a different syntax for the label. lab1: ; this will cause the lower order bit to be added lab2=. ; this will not cause the lower order bit to be added In some cases, it does not matter because in dwarf and debug tables the difference of two labels is used and in that case the lower order bits subtract each other out. To fix this, I have added to mcstreamer the notion of a debuglabel. The default is for label and debug label to be the same. So calling EmitLabel and EmitDebugLabel produce the same result. For various reasons, there is only one set of labels that needs to be modified for the mips exceptions to work. These are the "$eh_func_beginXXX" labels. Mips overrides the debug label suffix from ":" to "=." . This initial patch fixes exceptions. More changes most likely will be needed to DwarfCFException to make all of this work for actual debugging. These changes will be to emit debug labels in some places where a simple label is emitted now. Some historical discussion on this from gcc can be found at: http://gcc.gnu.org/ml/gcc-patches/2008-08/msg00623.html http://gcc.gnu.org/ml/gcc-patches/2008-11/msg01273.html llvm-svn: 170279
* X86: Add a couple of target-specific dag combines that turn VSELECTS into ↵Benjamin Kramer2012-12-155-18/+428
| | | | | | | | | | | psubus if possible. We match the pattern "x >= y ? x-y : 0" into "subus x, y" and two special cases if y is a constant. DAGCombiner canonicalizes those so we first have to undo the canonicalization for those cases. The pattern occurs in gzip when the loop vectorizer is enabled. Part of PR14613. llvm-svn: 170273
* Add a corollary test for PR14572. We got this code path correct already.Chandler Carruth2012-12-151-2/+18
| | | | llvm-svn: 170271
* Relax an overly aggressive assert to fix PR14572.Chandler Carruth2012-12-152-1/+17
| | | | | | The alloca width is based on the alloc size, not the type size. llvm-svn: 170270
* Make '-mtune=x86_64' assume fast unaligned memory accesses.Chandler Carruth2012-12-151-1/+2
| | | | | | | | | | | | | | Not all chips targeted by x86_64 have this feature, but a dramatically increasing number do. Specifying a chip-specific tuning parameter will continue to turn the feature on or off as appropriate for that particular chip, but the generic flag should try to achieve the best performance on the most widely available hardware. Today, the number of chips with fast UA access dwarfs those without in the x86-64 space. Note that this also brings LLVM's code generation for this '-march' flag more in line with that of modern GCCs. Reviewed by Dan Gohman. llvm-svn: 170269
* Actually update the grammar of this sentence to reflect the removal of CellSPU.Chandler Carruth2012-12-151-1/+1
| | | | llvm-svn: 170268
* Revert r170246, "Enable the loop vectorizer by default."NAKAMURA Takumi2012-12-151-1/+1
| | | | llvm-svn: 170267
* This code implements most of mips16 hardfloat as it is done by gcc.Reed Kotler2012-12-153-0/+427
| | | | | | | | | | | | | | | | In this case, essentially it is soft float with different library routines. The next step will be to make this fully interoperational with mips32 floating point and that requires creating stubs for functions with signatures that contain floating point types. I have a more sophisticated design for mips16 hardfloat which I hope to implement at a later time that directly does floating point without the need for function calls. The mips16 encoding has no floating point instructions so one needs to switch to mips32 mode to execute floating point instructions. llvm-svn: 170259
* To simplify some code move the unit emission into the holders.Eric Christopher2012-12-152-23/+34
| | | | | | Make emitDIE public accordingly. No functional change. llvm-svn: 170258
* Use begin and end label names from the section for info.Eric Christopher2012-12-151-7/+8
| | | | llvm-svn: 170257
* Make sure the alternate PC+imm syntax of LDR instruction with a smallKevin Enderby2012-12-142-1/+10
| | | | | | | | immediate generates the narrow version. Needed when doing round-trip assemble/disassemble testing using the alternate syntax that specifies 'pc' directly. llvm-svn: 170255
* Add back FoldOpIntoPhi optimizations with fix. Included test cases to help ↵Michael Ilseman2012-12-142-0/+43
| | | | | | catch these errors and to test the presence of the optimization itself llvm-svn: 170248
* Enable the loop vectorizer by default.Nadav Rotem2012-12-141-1/+1
| | | | llvm-svn: 170246
* TypeLegalizer: Do not generate target specific nodes with illegal types, ↵Nadav Rotem2012-12-142-0/+25
| | | | | | because we cant type-legalize them. llvm-svn: 170245
* Release notes for dragonegg 3.2.Duncan Sands2012-12-141-1/+4
| | | | llvm-svn: 170243
* Fix a crash in ValueTracking on vectors of pointers. Nadav Rotem2012-12-142-1/+11
| | | | llvm-svn: 170240
* This patch removes some nondeterminism from direct object file outputBill Schmidt2012-12-142-4/+45
| | | | | | | | | | for TLS dynamic models on 64-bit PowerPC ELF. The default sort routine for relocations only sorts on the r_offset field; but with TLS, there can be two relocations with the same r_offset. For PowerPC, this patch sorts secondarily on descending r_type, which matches the behavior expected by the linker. llvm-svn: 170237
* Add more reset methods to make all objects that the backend may use for ↵Pedro Artigas2012-12-147-1/+40
| | | | | | outputting code have a reset, some are not used but were declared for completeness llvm-svn: 170227
* rdar://12753946Shuxin Yang2012-12-142-6/+66
| | | | | | Implement rule : "x * (select cond 1.0, 0.0) -> select cond x, 0.0" llvm-svn: 170226
* [CMake] Move libxml2 stuff from clang to llvm/cmake.NAKAMURA Takumi2012-12-142-0/+8
| | | | llvm-svn: 170225
* This patch improves the 64-bit PowerPC InitialExec TLS support by providingBill Schmidt2012-12-1413-48/+67
| | | | | | | | | | | | | | | | | | | | | | | for a wider range of GOT entries that can hold thread-relative offsets. This matches the behavior of GCC, which was not documented in the PPC64 TLS ABI. The ABI will be updated with the new code sequence. Former sequence: ld 9,x@got@tprel(2) add 9,9,x@tls New sequence: addis 9,2,x@got@tprel@ha ld 9,x@got@tprel@l(9) add 9,9,x@tls Note that a linker optimization exists to transform the new sequence into the shorter sequence when appropriate, by replacing the addis with a nop and modifying the base register and relocation type of the ld. llvm-svn: 170209
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