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* AArch64: print NEON lists with a space.Tim Northover2014-04-2415-1522/+1522
| | | | | | | This matches ARM64 behaviour, which I think is clearer. It also puts all the churn from that difference into one easily ignored commit. llvm-svn: 207116
* [asan] Use MCInstrInfo in inline asm instrumentation.Evgeniy Stepanov2014-04-243-26/+17
| | | | | | Patch by Yuri Gorshenin. llvm-svn: 207115
* AArch64/ARM64: enable remaining MC elf tests.Tim Northover2014-04-243-0/+7
| | | | llvm-svn: 207112
* AArch64/ARM64: allow negative addends, at least on ELF.Tim Northover2014-04-242-14/+20
| | | | llvm-svn: 207111
* ARM64: support relocated "TBZ/TBNZ" instructions.Tim Northover2014-04-242-0/+5
| | | | llvm-svn: 207110
* AArch64/ARM64: support relocated ADR instructionTim Northover2014-04-242-1/+5
| | | | llvm-svn: 207109
* AArch64/ARM64: add support for :abs_gN_s: MOVZ modifiersTim Northover2014-04-247-0/+36
| | | | | | We only need assembly support, so it's fairly easy. llvm-svn: 207108
* ARM64: shut up warning about variable only used in assert.Tim Northover2014-04-241-0/+1
| | | | llvm-svn: 207106
* AArch64/ARM64: disentangle the "B.CC" and "LDR lit" operandsTim Northover2014-04-2414-54/+97
| | | | | | | | | | | | | These can have different relocations in ELF. In particular both: b.eq global ldr x0, global are valid, giving different relocations. The only possible way to distinguish them is via a different fixup, so the operands had to be separated throughout the backend. llvm-svn: 207105
* AArch64/ARM64: enable some MC tests on ARM64Tim Northover2014-04-246-2/+8
| | | | | | | This will also (as with CodeGen) disable testing when the ARM64 backend is not present. llvm-svn: 207104
* AArch64/ARM64: port bitfield test to ARM64.Tim Northover2014-04-241-12/+20
| | | | llvm-svn: 207103
* AArch64/ARM64: implement BFI optimisationTim Northover2014-04-243-62/+161
| | | | | | | | | | | ARM64 was not producing pure BFI instructions for bitfield insertion operations, unlike AArch64. The approach had to be a little different (in ISelDAGToDAG rather than ISelLowering), and the outcomes aren't identical but hopefully this gives it similar power. This should address PR19424. llvm-svn: 207102
* AArch64/ARM64: port more testsTim Northover2014-04-244-0/+77
| | | | llvm-svn: 207101
* [LCG] Incorporate the core trick of improvements on the naive Tarjan'sChandler Carruth2014-04-242-45/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | algorithm here: http://dl.acm.org/citation.cfm?id=177301. The idea of isolating the roots has even more relevance when using the stack not just to implement the DFS but also to implement the recursive step. Because we use it for the recursive step, to isolate the roots we need to maintain two stacks: one for our recursive DFS walk, and another of the nodes that have been walked. The nice thing is that the latter will be half the size. It also fixes a complete hack where we scanned backwards over the stack to find the next potential-root to continue processing. Now that is always the top of the DFS stack. While this is a really nice improvement already (IMO) it further opens the door for two important simplifications: 1) De-duplicating some of the code across the two different walks. I've actually made the duplication a bit worse in some senses with this patch because the two are starting to converge. 2) Dramatically simplifying the loop structures of both walks. I wanted to do those separately as they'll be essentially *just* CFG restructuring. This patch on the other hand actually uses different datastructures to implement the algorithm itself. llvm-svn: 207098
* [LCG] Rotate logic applied to the top of the DFSStack to instead beChandler Carruth2014-04-241-25/+24
| | | | | | | | | | | | | applied prior to pushing a node onto the DFSStack. This is the first step toward avoiding the stack entirely for leaf nodes. It also simplifies things a bit and I think is pointing the way toward factoring some more of the shared logic out of the two implementations. It is also making it more obvious how to restructure the loops themselves to be a bit easier to read (although no different in terms of functionality). llvm-svn: 207095
* [LCG] Re-order expectations to provide more useful output when debuggingChandler Carruth2014-04-241-4/+4
| | | | | | | an issue. This way you see that the number of nodes was wrong before a crash due to accessing too many nodes. llvm-svn: 207094
* [asan] Fix instrumentation of x86 intel syntax inline assembly.Evgeniy Stepanov2014-04-242-15/+86
| | | | | | Patch by Yuri Gorshenin. llvm-svn: 207092
* [LCG] Switch the parent SCC tracking from a SmallSetVector toChandler Carruth2014-04-242-4/+4
| | | | | | | | | | | | | | | | a SmallPtrSet. Currently, there is no need for stable iteration in this dimension, and I now thing there won't need to be going forward. If this is ever re-introduced in any form, it needs to not be a SetVector based solution because removal cannot be linear. There will be many SCCs with large numbers of parents. When encountering these, the incremental SCC update for intra-SCC edge removal was quadratic due to linear removal (kind of). I'm really hoping we can avoid having an ordering property here at all though... llvm-svn: 207091
* [LCG] We don't actually need a set in each SCC to track the nodes. WeChandler Carruth2014-04-242-8/+1
| | | | | | | can use the node -> SCC mapping in the top-level graph to test this on the rare occasions we need it. llvm-svn: 207090
* [CLNUP] Test commit. Remove newline.Zinovy Nis2014-04-241-2/+1
| | | | llvm-svn: 207089
* X86: Emit test instead of constant shift + compare if the shift result is ↵Benjamin Kramer2014-04-242-26/+72
| | | | | | | | | | | | | | | | | | unused. This allows us to compile return (mask & 0x8 ? a : b); into testb $8, %dil cmovnel %edx, %esi instead of andl $8, %edi shrl $3, %edi cmovnel %edx, %esi which we formed previously because dag combiner canonicalizes setcc of and into shift. llvm-svn: 207088
* [LCG] Switch the SCC's parent iterators to be value iterators ratherChandler Carruth2014-04-242-2/+3
| | | | | | than pointer iterators. llvm-svn: 207086
* Allow vectorization of few missed llvm intrinsic calls in BBVectorizor by ↵Karthik Bhat2014-04-242-1/+226
| | | | | | handling them in isVectorizableIntrinsic function. llvm-svn: 207085
* [ADT] Attempt to appease another MSVC oddity by moving the injectedChandler Carruth2014-04-241-3/+5
| | | | | | class name usage into a context we can put typename on it. llvm-svn: 207084
* [C++] Use 'nullptr'.Craig Topper2014-04-2452-291/+299
| | | | llvm-svn: 207083
* [ADT] Try to appease MSVC by sinking the enable_if from a defaultChandler Carruth2014-04-241-5/+6
| | | | | | template argument to a default argument to the constructor. llvm-svn: 207082
* Fix for PR18921, "vmov" part.Stepan Dyatkovskiy2014-04-245-4/+236
| | | | | | | | | | | | | | | | | | | | | | | Added support for bytes replication feature, so it could be GAS compatible. E.g. instructions below: "vmov.i32 d0, 0xffffffff" "vmvn.i32 d0, 0xabababab" "vmov.i32 d0, 0xabababab" "vmov.i16 d0, 0xabab" are incorrect, but we could deal with such cases. For first one we should emit: "vmov.i8 d0, 0xff" For second one ("vmvn"): "vmov.i8 d0, 0x54" For last two instructions it should emit: "vmov.i8 d0, 0xab" P.S.: In ARMAsmParser.cpp I have also fixed few nearby style issues in old code. Just for keeping method bodies in harmony with themselves. llvm-svn: 207080
* Use the shiny new iterator adaptor tool to implement theChandler Carruth2014-04-241-54/+7
| | | | | | value_op_iterator. llvm-svn: 207078
* [ADT] Factor out the facade aspect of the iterator_adaptor_base into itsChandler Carruth2014-04-241-54/+89
| | | | | | | | | own CRTP base class for more general purpose use. Add some clarifying comments for the exact way in which the adaptor uses it. Hopefully this will help us write increasingly full featured iterators. This is becoming important as they start to be used heavily inside of ranges. llvm-svn: 207072
* [ADT] Add a generic iterator utility for adapting iterators much likeChandler Carruth2014-04-243-1/+206
| | | | | | | | | | | | | | | | | | | | | | | | | Boost's iterator_adaptor, and a specific adaptor which iterates over pointees when wrapped around an iterator over pointers. This is the result of a long discussion on IRC with Duncan Smith, Dave Blaikie, Richard Smith, and myself. Essentially, I could use some subset of the iterator facade facilities often used from Boost, and everyone seemed interested in having the functionality in a reasonably generic form. I've tried to strike a balance between the pragmatism and the established Boost design. The primary differences are: 1) Delegating to the standard iterator interface names rather than special names that then make up a second iterator-like API. 2) Using the name 'pointee_iterator' which seems more clear than 'indirect_iterator'. The whole business of calling the '*p' operation 'pointer indirection' in the standard is ... quite confusing. And 'dereference' is no better of a term for moving from a pointer to a reference. Hoping Duncan, and others continue to provide comments on this until we've got a nice, minimal abstraction. llvm-svn: 207069
* Remove unused parameterDavid Blaikie2014-04-242-5/+4
| | | | llvm-svn: 207061
* Remove the intermediate AccelTypes maps in DWARF units.David Blaikie2014-04-245-37/+23
| | | | llvm-svn: 207060
* Remove the intermediate AccelNamespace maps in DWARF units.David Blaikie2014-04-244-29/+17
| | | | llvm-svn: 207059
* [InstCombine][x86] Constant fold psll intrinsics.Michael J. Spencer2014-04-242-0/+151
| | | | | | | | | | | | This excludes avx512 as I don't have hardware to verify. It excludes _dq variants because they are represented in the IR as <{2,4} x i64> when it's actually a byte shift of the entire i{128,265}. This also excludes _dq_bs as they aren't at all supported by the backend. There are also no corresponding instructions in the ISA. I have no idea why they exist... llvm-svn: 207058
* Remove the intermediate AccelObjC maps in DWARF unitsDavid Blaikie2014-04-244-32/+17
| | | | llvm-svn: 207057
* Optimize some special cases for SSE4a insertqiFilipe Cabecinhas2014-04-242-0/+164
| | | | | | | | | | | | | | | | | | | | Summary: Since the upper 64 bits of the destination register are undefined when performing this operation, we can substitute it and let the optimizer figure out that only a copy is needed. Also added range merging, if an instruction copies a range that can be merged with a previous copied range. Added test cases for both optimizations. Reviewers: grosbach, nadav CC: llvm-commits Differential Revision: http://reviews.llvm.org/D3357 llvm-svn: 207055
* Handle addrspacecast when looking at memcpys from globalsMatt Arsenault2014-04-242-7/+69
| | | | llvm-svn: 207054
* [LCG] Normalize the post-order SCC iterator to just iterate over the SCCChandler Carruth2014-04-234-33/+32
| | | | | | values rather than having pointers in weird places. llvm-svn: 207053
* [LCG] Remove two unused typedefs from the iterators.Chandler Carruth2014-04-231-4/+0
| | | | llvm-svn: 207052
* And actually use the DwarfDebug::AccelNames to emit the names.David Blaikie2014-04-232-18/+2
| | | | | | Fix for r207049 which would've emitted no accelerated names at all... llvm-svn: 207051
* More formatting...David Blaikie2014-04-231-1/+2
| | | | llvm-svn: 207050
* Remove intermediate accelerator table for names.David Blaikie2014-04-234-23/+27
| | | | | | (similar changes coming for the other accelerator tables) llvm-svn: 207049
* [LCG] Switch the primary node iterator to be a *much* more normal C++Chandler Carruth2014-04-233-93/+86
| | | | | | iterator, returning a Node by reference on dereference. llvm-svn: 207048
* [LCG] Make the insertion and query paths into the LCG which cannot failChandler Carruth2014-04-232-11/+11
| | | | | | | | return references to better model this property. No functionality changed. llvm-svn: 207047
* [LCG] Switch the SCC lookup to be in terms of call graph nodes ratherChandler Carruth2014-04-233-45/+45
| | | | | | | | | | than functions. So far, this access pattern is *much* more common. It seems likely that any user of this interface is going to have nodes at the point that they are querying the SCCs. No functionality changed. llvm-svn: 207045
* DwarfAccelTable: Remove trivial dtor and simplify construction with an array.David Blaikie2014-04-233-10/+4
| | | | llvm-svn: 207044
* Use std::less instead of < in array_pod_sort's default comparator.Jordan Rose2014-04-231-5/+6
| | | | | | This makes array_pod_sort portably safe to use with pointers. llvm-svn: 207043
* [LCG] Switch the primary SCC building code to use the negative low-linkChandler Carruth2014-04-231-2/+4
| | | | | | | | | | | | | | | values rather than an expensive dense map query to test whether children have already been popped into an SCC. This matches the incremental SCC building code. I've also included the assert that I put there but updated both of their text. No functionality changed here. I still don't have any great ideas for sharing the code between the two implementations, but I may try a brute-force approach to factoring it at some point. llvm-svn: 207042
* MC: disable test on thumbv7-windowsSaleem Abdulrasool2014-04-231-1/+0
| | | | | | | This is dependent on changes that are not fully ready to be merged yet (WoA object file emission). The test can be re-enabled for that target later. llvm-svn: 207038
* llvm-cov: Add support for gcov's --long-file-names optionJustin Bogner2014-04-236-10/+46
| | | | | | | | GCOV provides an option to prepend output file names with the source file name, to disambiguate between covered data that's included from multiple sources. Add a flag to llvm-cov that does the same. llvm-svn: 207035
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