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* Keep VC++ happy.Jeff Cohen2005-12-181-0/+1
| | | | llvm-svn: 24835
* This is handled by the autogen'd codeChris Lattner2005-12-181-1/+0
| | | | llvm-svn: 24834
* Handle basic block nodesChris Lattner2005-12-181-0/+1
| | | | llvm-svn: 24833
* Change return lowering so that we can autogen the matching code.Chris Lattner2005-12-182-30/+25
| | | | llvm-svn: 24832
* Add an accessorChris Lattner2005-12-181-1/+11
| | | | llvm-svn: 24831
* Implement Calls for V8. This would be completely autogenerated except forChris Lattner2005-12-182-15/+257
| | | | | | | a small bug in tblgen. When that is fixed, we can remove the ISD::Call case in Select. llvm-svn: 24830
* More fixes for Selection of copyto/fromreg with a flagChris Lattner2005-12-181-11/+10
| | | | llvm-svn: 24829
* More corrections for flagged copyto/from regChris Lattner2005-12-181-8/+11
| | | | llvm-svn: 24828
* Select copytoreg and copyfromreg nodes that have flag operands correctly.Chris Lattner2005-12-181-9/+37
| | | | llvm-svn: 24827
* legalize copytoreg and copyfromreg nodes that have flag operands correctly.Chris Lattner2005-12-181-11/+34
| | | | llvm-svn: 24826
* Implement the full V8 ABI for incoming arguments.Chris Lattner2005-12-182-28/+143
| | | | llvm-svn: 24825
* Push ops list, asm string, and pattern all the way up to InstV8. Move theChris Lattner2005-12-182-48/+28
| | | | | | InstV8 class to the InstrFormats file where it belongs. llvm-svn: 24824
* Give V8 select_cc, in the spirit of the PPC backendChris Lattner2005-12-182-32/+189
| | | | llvm-svn: 24823
* remove some unused instructionsChris Lattner2005-12-181-12/+0
| | | | llvm-svn: 24822
* V8 doesn't have FP extloadChris Lattner2005-12-181-0/+2
| | | | llvm-svn: 24821
* simplifications, fix typoChris Lattner2005-12-181-6/+5
| | | | llvm-svn: 24820
* add a node, for completenessChris Lattner2005-12-181-0/+2
| | | | llvm-svn: 24819
* Add frameindex supportChris Lattner2005-12-182-26/+96
| | | | | | | Add support for copying (e.g. returning) doubles Add support for F<->I instructions llvm-svn: 24818
* Tighten up some checksChris Lattner2005-12-181-5/+1
| | | | llvm-svn: 24817
* Fix a bug Sabre was having where the DAG root was a group. The group dominatorJim Laskey2005-12-181-1/+6
| | | | | | needed to be added to the ordering list, not the first member of the group. llvm-svn: 24816
* Groups were not emitted if the dominator node and the node in the ordering listJim Laskey2005-12-181-10/+6
| | | | | | were not the same node. Ultimately the test was bogus. llvm-svn: 24815
* Since extload can also be used by FP, split STDIntExtLoad into two parts,Nate Begeman2005-12-181-2/+5
| | | | | | | one for use with extload, one for use with sextload and zextload, which are integer only. llvm-svn: 24814
* Add constant pool support, including folding into addresses.Chris Lattner2005-12-183-2/+24
| | | | | | Pretty print addresses a bit, to not print [%r1+%g0]: just print [%r1] llvm-svn: 24813
* Teach the addressing mode stuff to fold "%lo" into 'ri' addressing modes,Chris Lattner2005-12-182-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | allowing us to compile this: to this: %G1 = external global int %G2 = external global int void %test() { %X = load int* %G1 store int %X, int* %G2 ret void } test: save -96, %sp, %sp sethi %hi(G1), %l0 ld [%l0+%lo(G1)], %l0 sethi %hi(G2), %l1 st %l0, [%l1+%lo(G2)] restore %g0, %g0, %g0 retl nop instead of this: test: save -96, %sp, %sp sethi %hi(G1), %l0 or %g0, %lo(G1), %l1 ld [%l1+%l0], %l0 sethi %hi(G2), %l1 or %g0, %lo(G2), %l2 st %l0, [%l2+%l1] restore %g0, %g0, %g0 retl nop llvm-svn: 24812
* Add initial support for global variables, and fix a bug in addr mode selectionChris Lattner2005-12-182-3/+21
| | | | | | where we didn't select the operands. llvm-svn: 24811
* Claiming that branch targets are registers is not very wholesome. Change themChris Lattner2005-12-181-51/+56
| | | | | | to be basic blocks. Also, add uncond branches. llvm-svn: 24810
* Add unordered comparisonsChris Lattner2005-12-181-13/+8
| | | | llvm-svn: 24809
* Add patterns to the rest of the int condbranches and some of the fp branchesChris Lattner2005-12-181-23/+46
| | | | llvm-svn: 24808
* Add initial conditional branch support. This doesn't actually work yet dueChris Lattner2005-12-184-46/+160
| | | | | | to a bug in the scheduler. llvm-svn: 24807
* Simplify codeChris Lattner2005-12-181-7/+2
| | | | llvm-svn: 24806
* Eliminate CMPri, which is a synonym for SUBCCriChris Lattner2005-12-172-8/+3
| | | | llvm-svn: 24805
* allow custom expansion of BR_CCChris Lattner2005-12-171-11/+25
| | | | llvm-svn: 24804
* add fneg,fabs,fsqrt instructionsChris Lattner2005-12-172-4/+16
| | | | llvm-svn: 24803
* Add patterns for fround/fextend and the funny fsmuld instructionChris Lattner2005-12-171-4/+8
| | | | llvm-svn: 24802
* Add FP +,-,*,/Chris Lattner2005-12-171-8/+16
| | | | llvm-svn: 24801
* Give patterns to F3_3 instructionsChris Lattner2005-12-172-21/+22
| | | | llvm-svn: 24800
* Implement 64-bit add/sub, make sure to receive and return 64-bit args withChris Lattner2005-12-171-4/+32
| | | | | | the right halves in the right regs llvm-svn: 24799
* implement div and remChris Lattner2005-12-171-0/+26
| | | | llvm-svn: 24798
* implement MULHU/MULHS for 64-bit multipliesChris Lattner2005-12-171-0/+11
| | | | llvm-svn: 24797
* Add patterns for multiply, simplify Y register handling stuff, add RDY ↵Chris Lattner2005-12-173-17/+17
| | | | | | instruction llvm-svn: 24796
* Make the addressing modes smarterChris Lattner2005-12-172-10/+21
| | | | llvm-svn: 24795
* remove some unused instructionsChris Lattner2005-12-171-81/+6
| | | | llvm-svn: 24794
* add andn/orn/xorn patterns. This allows us to compile this:Chris Lattner2005-12-171-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | long %test(ubyte, short, long %X, long %Y) { %A = xor long %X, -1 %B = and long %Y, %A ret long %B } to this: test: save -96, %sp, %sp andn %i4, %i2, %i0 andn %i5, %i3, %i1 restore %g0, %g0, %g0 retl nop instead of this: test: save -96, %sp, %sp xor %i2, -1, %l0 xor %i3, -1, %l1 and %i4, %l0, %i0 and %i5, %l1, %i1 restore %g0, %g0, %g0 retl nop The simpleisel emits: :( test: save -96, %sp, %sp or %g0, -1, %l0 or %g0, -1, %l0 or %g0, -1, %l0 or %g0, -1, %l1 xor %i2, %l0, %l0 xor %i3, %l1, %l1 and %i4, %l0, %i0 and %i5, %l1, %i1 restore %g0, %g0, %g0 retl nop llvm-svn: 24793
* Add support for 64-bit argumentsChris Lattner2005-12-171-0/+12
| | | | llvm-svn: 24792
* Sparc doesn't have sext_inregChris Lattner2005-12-171-0/+5
| | | | llvm-svn: 24791
* add patterns for FP storesChris Lattner2005-12-171-20/+12
| | | | llvm-svn: 24790
* Add [reg+reg] integer storesChris Lattner2005-12-171-0/+15
| | | | llvm-svn: 24789
* Add store patternsChris Lattner2005-12-171-3/+6
| | | | llvm-svn: 24788
* add truncstoreChris Lattner2005-12-171-3/+9
| | | | llvm-svn: 24787
* add fp load patterns, switch rest of loads and stores to use addrmodesChris Lattner2005-12-171-30/+28
| | | | llvm-svn: 24786
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