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* autoconf: fix clang detectionDylan Noblesmith2012-02-042-2/+2
| | | | | | | Now this works with and without --with-clang-srcdir, with and without an out-of-tree build. llvm-svn: 149749
* Emit new property tag.Devang Patel2012-02-041-1/+29
| | | | llvm-svn: 149737
* Update llvm debug version to support new structure and tag for Objective-C ↵Devang Patel2012-02-043-3/+16
| | | | | | property's debug info. llvm-svn: 149736
* Introduce DIObjCProperty. This will be used to encode objective-c property.Devang Patel2012-02-044-0/+72
| | | | llvm-svn: 149732
* [fast-isel] HandlePHINodesInSuccessorBlocks() can promite i8 and i16 types too.Chad Rosier2012-02-042-2/+46
| | | | llvm-svn: 149730
* Update to the new EH system...remove OLD EH code.Bill Wendling2012-02-041-88/+4
| | | | llvm-svn: 149728
* Drop ZeroIndex and InvalidIndex.Jakob Stoklund Olesen2012-02-042-13/+0
| | | | | | | They are not used any more. Simply use SlotIndex() to get an invalid index. llvm-svn: 149727
* Add new tag and an attribute to support debug info for objective-c property.Devang Patel2012-02-032-0/+4
| | | | llvm-svn: 149724
* Trim headers.Jakob Stoklund Olesen2012-02-031-8/+0
| | | | llvm-svn: 149722
* Delete some dead code.Jakob Stoklund Olesen2012-02-032-8/+0
| | | | llvm-svn: 149717
* [fast-isel] Add support for URem.Chad Rosier2012-02-031-8/+10
| | | | llvm-svn: 149716
* Handle register mask operands in setPhysRegsDeadExcept().Jakob Stoklund Olesen2012-02-032-0/+15
| | | | | | | | | | | Calls that use register mask operands don't have implicit defs for returned values. The register mask operand handles the call clobber, but it always behaves like a set of dead defs. Add live implicit defs for any implicitly defined physregs that are actually used. llvm-svn: 149715
* [fast-isel] Rename isZExt to isSigned. No functional change intended.Chad Rosier2012-02-031-13/+14
| | | | llvm-svn: 149714
* Increment DFAStateEntryTable index for sentinel entry.Brendon Cahoon2012-02-031-1/+3
| | | | | | | | | When adding the {-1, -1} entry to the DFAStateInputTable, we need to increment the index used to populate the DFAStateEntryTable. Otherwise, the entry table will be off by one for each transition after the {-1, -1} entry. PR11908. llvm-svn: 149713
* [fast-isel] Add support for UDIV.Chad Rosier2012-02-031-8/+10
| | | | llvm-svn: 149712
* ArrayRef'ize MI::setPhysRegsDeadExcept().Jakob Stoklund Olesen2012-02-032-4/+5
| | | | llvm-svn: 149709
* Handle all live physreg defs in the same place.Jakob Stoklund Olesen2012-02-032-44/+47
| | | | | | | | | | | SelectionDAG has 4 different ways of passing physreg defs to users. Collect all of the uses at the same time, and pass all of them to MI->setPhysRegsDeadExcept() to mark the remaining defs dead. The setPhysRegsDeadExcept() function will soon add the required implicit-defs to instructions with register mask operands. llvm-svn: 149708
* [fast-isel] Add support for FPToUI. Also add test cases for FPToSI.Chad Rosier2012-02-032-6/+60
| | | | llvm-svn: 149706
* Initialize all common codegen passes before configuration so we can use ↵Andrew Trick2012-02-032-2/+8
| | | | | | their PassIDs. llvm-svn: 149705
* [fast-isel] Add support for selecting UIToFP.Chad Rosier2012-02-032-6/+102
| | | | llvm-svn: 149704
* Simplify some GEP checks in the verifier.Duncan Sands2012-02-031-4/+2
| | | | llvm-svn: 149698
* The type-legalizer often scalarizes code. One of the common patterns is ↵Nadav Rotem2012-02-033-1/+43
| | | | | | | | | extract-and-truncate. In this patch we optimize this pattern and convert the sequence into extract op of a narrow type. This allows the BUILD_VECTOR dag optimizations to construct efficient shuffle operations in many cases. llvm-svn: 149692
* Remove getShuffleVPERMILPImmediate function, getShuffleSHUFImmediate ↵Craig Topper2012-02-031-30/+1
| | | | | | performs the same calculation. llvm-svn: 149683
* Allow command-line overrides of the target triple with the Mach-OCameron Zwarich2012-02-031-19/+20
| | | | | | disassembler, just like the generic disassembler. llvm-svn: 149681
* Remove unnecessary qualification on 256-bit vector handling in ↵Craig Topper2012-02-031-2/+2
| | | | | | LowerBUILD_VECTOR. Condition was already guaranteed by earlier code. llvm-svn: 149680
* Add auto upgrade support for x86 pcmpgt/pcmpeq intrinics removed in r149367.Craig Topper2012-02-031-3/+40
| | | | llvm-svn: 149678
* Do the same fix as r149667, but for the Mach-O disassembler.Cameron Zwarich2012-02-031-0/+4
| | | | llvm-svn: 149674
* Added TargetPassConfig. The first little step toward configuring codegen passes.Andrew Trick2012-02-0325-268/+565
| | | | | | | | | | | Allows command line overrides to be centralized in LLVMTargetMachine.cpp. LLVMTargetMachine can intercept common passes and give precedence to command line overrides. Allows adding "internal" target configuration options without touching TargetOptions. Encapsulates the PassManager. Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs. Allows modifying the target configuration hooks without rebuilding the world. llvm-svn: 149672
* whitespaceAndrew Trick2012-02-038-47/+47
| | | | llvm-svn: 149671
* Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which isAkira Hatanaka2012-02-0314-5/+85
| | | | | | | | needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. llvm-svn: 149668
* Fix llvm-objdump disassembly for interesting Mach-O binaries, e.g. any MacOSCameron Zwarich2012-02-031-0/+2
| | | | | | | dylib. This regressed with r145408. I will try to make a test case and add it so that this doesn't happen again. llvm-svn: 149667
* Incorporate suggestions Chad, Jakob and Evan's suggestions on r149957.Lang Hames2012-02-031-22/+33
| | | | llvm-svn: 149655
* Fix SSAUpdaterImpl's RecordMatchingPHI to record exactly theDan Gohman2012-02-032-32/+88
| | | | | | | | | | PHI nodes which were matched, rather than climbing up the original PHI node's operands to rediscover PHI nodes for recording, since the PHI nodes found that are not necessarily part of the matched set. This fixes rdar://10589171. llvm-svn: 149654
* Replace the old --with-cxx-* configure options with a single ↵Rafael Espindola2012-02-037-189/+45
| | | | | | | | | --with-gcc-toolchain that just uses the new toolchain probing logic. This fixes linking with -m32 on 64 bit systems (the /32 dir was not being added to the search). llvm-svn: 149651
* Narrow test further. Make bot and test happy.Jim Grosbach2012-02-031-1/+3
| | | | llvm-svn: 149650
* Tidy up. Trailing whitespace.Jim Grosbach2012-02-031-55/+55
| | | | llvm-svn: 149649
* Restrict InstCombine from converting varargs to or from fixed args.Jim Grosbach2012-02-031-0/+7
| | | | | | More targetted fix replacing d0e277d272d517ca1cda368267d199f0da7cad95. llvm-svn: 149648
* Revert "Disable InstCombine unsafe folding bitcasts of calls w/ varargs."Jim Grosbach2012-02-033-5/+51
| | | | | | This reverts commit d0e277d272d517ca1cda368267d199f0da7cad95. llvm-svn: 149647
* Require non-NULL register masks.Jakob Stoklund Olesen2012-02-026-15/+12
| | | | | | | It doesn't seem worthwhile to give meaning to a NULL register mask pointer. It complicates all the code using register mask operands. llvm-svn: 149646
* build/make: Ensure make clean removes the LLVMBuild makefile fragment.Daniel Dunbar2012-02-021-0/+4
| | | | llvm-svn: 149643
* build/Make: Add missing dependency, LLVMBuild makefile fragment implicitly ↵Daniel Dunbar2012-02-021-1/+2
| | | | | | depends on Makefile.config. llvm-svn: 149642
* Add pseudo-registers for pairs, triples, and quads of D registers.Jakob Stoklund Olesen2012-02-021-15/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | NEON loads and stores accept single and double spaced pairs, triples, and quads of D registers. This patch adds new register classes to accurately model those constraints: Dn, Dn+1 Dn, Dn+2 ---------------------- DPair DPairSpc DTriple DTripleSpc DQuad DQuadSpc Also extend the existing QQ and QQQQ register classes to contains all Q pairs and quads instead of just the aligned ones. These new register classes will make it possible to accurately model constraints on NEON loads and stores, and we can get rid of all the NEON pseudo-instructions. The late scheduler will be able to accurately model instruction dependencies from the explicit operands. This more than doubles the number of ARM registers, but the backend passes are quite good at handling this. The llc -O0 compile time only regresses by 1.5%. Future work on register mask operands will recover this regression. llvm-svn: 149640
* Unix line endingsMatt Beaumont-Gay2012-02-022-33/+33
| | | | llvm-svn: 149615
* BBVectorize: Simplify code, no functionality change.Benjamin Kramer2012-02-021-9/+3
| | | | | | Also silences warnings about bodyless for loops. llvm-svn: 149612
* Minor changes from review.Hal Finkel2012-02-021-19/+17
| | | | | | As suggested by Nick Lewycky, the tree traversal queues have been changed to SmallVectors and the associated loops have been rotated. Also, an 80-col violation was fixed. llvm-svn: 149607
* Move test/CodeGen/Generic/2012-02-01-CoalescerBug.ll to CodeGen/ARM, for ↵NAKAMURA Takumi2012-02-021-0/+0
| | | | | | | | now. It requires TARGETS=arm. I cannot reproduce a fixed issue with other targets. llvm-svn: 149604
* Minor change in signature of the getZeroVector() Elena Demikhovsky2012-02-021-30/+21
| | | | llvm-svn: 149601
* Optimization for SIGN_EXTEND operation on AVX.Elena Demikhovsky2012-02-025-0/+84
| | | | | | | Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32 extensions. llvm-svn: 149600
* Unbreak the MSVC build.Francois Pichet2012-02-021-1/+1
| | | | llvm-svn: 149599
* Re-apply the coalescer fix from r149147. Commit r149597 should have fixed ↵Lang Hames2012-02-021-0/+24
| | | | | | the llvm-gcc and clang self-host issues. llvm-svn: 149598
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