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* Fixing a type width warning with MSVC.Aaron Ballman2012-09-091-1/+1
| | | | llvm-svn: 163481
* DSE: Poking holes into a SetVector is expensive, avoid it if possible.Benjamin Kramer2012-09-091-5/+5
| | | | llvm-svn: 163480
* LiveVariables: Compute a set of defs and kills to speed up updating LV ↵Benjamin Kramer2012-09-091-4/+30
| | | | | | | | | | | | | | | during critical edge splitting. Previously we checked if the register is def'd in a block via the def/use list a nd walked the list of kills to check if the register is killed in a block. Both of these checks can be made much cheaper by walking the block first and recording all defs and kills. This reduces the compile time of the test case from PR13651 from 40s to 15s at -O2. The compile time is still dominated by LV updating but now the main culprit is SparseBitVector's slowness. llvm-svn: 163478
* Add instruction selection for ffloor of vectors when SSE4.1 or AVX is enabled.Craig Topper2012-09-083-20/+79
| | | | llvm-svn: 163473
* lit: Util.which(): Use os.path.isfile() instead of os.path.exists(), or it ↵NAKAMURA Takumi2012-09-081-1/+1
| | | | | | | | hits to the directory. For example, which('loop-convert') returns 'loop-convert' when the directory 'loop-convert' exists. llvm-svn: 163469
* Use 256-bit alignment for constant pool value for 256-bit vector FNEG lowering.Craig Topper2012-09-081-2/+3
| | | | llvm-svn: 163463
* Add support for lowering FABS of vector types.Craig Topper2012-09-082-12/+63
| | | | llvm-svn: 163461
* Set operation action for FFLOOR to Expand for all vector types for X86. Set ↵Craig Topper2012-09-083-0/+33
| | | | | | FFLOOR of v4f32 to Expand for ARM. v2f64 was already correct. llvm-svn: 163458
* Revert "Add -exact-match option to FileCheck to allow clients to do exact ↵Ted Kremenek2012-09-081-5/+1
| | | | | | | | | matches without using regular expressions." Turns out I did not need it after all. If we find a use for it in the future, we can resurrect it. llvm-svn: 163457
* Add operator< for FoldingSetNodeID.Ted Kremenek2012-09-082-0/+27
| | | | llvm-svn: 163454
* Remove an incorrect assert during branch weight propagation.Andrew Trick2012-09-082-1/+37
| | | | | | Patch and test case by Alastair Murray! llvm-svn: 163437
* Refactored DFA generator. Merged transition class into state class.Anshuman Dasgupta2012-09-071-117/+51
| | | | | | Patch by Ivan Llopard! llvm-svn: 163424
* Add IRC handle entry to CREDITS.TXT as a test commit.Alex Rosenberg2012-09-071-2/+3
| | | | llvm-svn: 163423
* Correct an unfortunately necessary typo.Sandeep Patel2012-09-071-4/+4
| | | | llvm-svn: 163422
* Fix alignment of .comm and .lcomm on mingw32.Benjamin Kramer2012-09-079-17/+42
| | | | | | | | For some reason .lcomm uses byte alignment and .comm log2 alignment so we can't use the same setting for both. Fix this by reintroducing the LCOMM enum. I verified this against mingw's gcc. llvm-svn: 163420
* Initial relocations test for the Mips standalone assembler.Jack Carter2012-09-071-0/+41
| | | | | | | This is not an exhaustive set, but something we can build on. Contributer: Vladimir Medic llvm-svn: 163419
* Fix indent.Chad Rosier2012-09-071-2/+2
| | | | llvm-svn: 163416
* Contrary to what the documentation says, .lcomm alignment on COFF is in ↵Benjamin Kramer2012-09-071-1/+1
| | | | | | bytes, not power of 2. llvm-svn: 163405
* Update function names to conform to guidelines. No functional change intended.Chad Rosier2012-09-072-49/+48
| | | | llvm-svn: 163401
* Custom DAGCombine for and/or/xor are for all ARMs.Jakob Stoklund Olesen2012-09-071-6/+3
| | | | | | | The 'select' transformations apply to all ARM architectures and don't require hasV6T2Ops. llvm-svn: 163396
* MC: Overhaul handling of .lcommBenjamin Kramer2012-09-0714-38/+67
| | | | | | | | | | | | | - Darwin lied about not supporting .lcomm and turned it into zerofill in the asm parser. Push the zerofill-conversion down into macho-specific code. - This makes the tri-state LCOMMType enum superfluous, there are no targets without .lcomm. - Do proper error reporting when trying to use .lcomm with alignment on a target that doesn't support it. - .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2. - Fixes PR13755 (.lcomm crashes on ELF). llvm-svn: 163395
* PR13754: llvm-mc/x86 crashes on .cfi directives without the % prefix for ↵Benjamin Kramer2012-09-072-5/+24
| | | | | | | | | registers. gas accepts this and it seems to be common enough to be worth supporting. This doesn't affect the parsing of reg operands outside of .cfi directives. llvm-svn: 163390
* MipsAsmParser: Fix a couple of string use-after-frees and misuses of classof.Benjamin Kramer2012-09-071-8/+8
| | | | llvm-svn: 163383
* yet another attempt at fixing @OCAMLOPT@ for sed.Nuno Lopes2012-09-071-1/+1
| | | | | | Patch by Rick Foos. llvm-svn: 163380
* SimplifyCFG: ValidLookupTableConstant should be staticHans Wennborg2012-09-071-1/+1
| | | | llvm-svn: 163378
* Add -exact-match option to FileCheck to allow clients to do exact matches ↵Ted Kremenek2012-09-071-1/+5
| | | | | | without using regular expressions. llvm-svn: 163371
* Stop emitting lifetime region info when stack coloring is not enabled in O0Michael Liao2012-09-071-0/+6
| | | | | | - this should fix PR13780 llvm-svn: 163370
* The Mips standalone assembler aliased instruction support.Jack Carter2012-09-073-0/+47
| | | | | | | | | | | | | | The assembler can alias one instruction into another based on the operands. For example the jump instruction "J" takes and immediate operand, but if the operand is a register the assembler will change it into a jump register "JR" instruction. These changes are in the instruction td file. Test cases included Contributer: Vladimir Medic llvm-svn: 163368
* The Mips standalone assembler intial directive support.Jack Carter2012-09-072-0/+53
| | | | | | | | | | Actually these are just stubs for parsing the directives. Semantic support will come later. Test cases included Contributer: Vladimir Medic llvm-svn: 163364
* The Mips standalone assembler fpu instruction support.Jack Carter2012-09-074-7/+386
| | | | | | | Test cases included Contributer: Vladimir Medic llvm-svn: 163363
* Re-work bit/bits value resolving in tblgenMichael Liao2012-09-068-201/+250
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - This patch is inspired by the failure of the following code snippet which is used to convert enumerable values into encoding bits to improve the readability of td files. class S<int s> { bits<2> V = !if(!eq(s, 8), {0, 0}, !if(!eq(s, 16), {0, 1}, !if(!eq(s, 32), {1, 0}, !if(!eq(s, 64), {1, 1}, {?, ?})))); } Later, PR8330 is found to report not exactly the same bug relevant issue to bit/bits values. - Instead of resolving bit/bits values separately through resolveBitReference(), this patch adds getBit() for all Inits and resolves bit value by resolving plus getting the specified bit. This unifies the resolving of bit with other values and removes redundant logic for resolving bit only. In addition, BitsInit::resolveReferences() is optimized to take advantage of this origanization by resolving VarBitInit's variable reference first and then getting bits from it. - The type interference in '!if' operator is revised to support possible combinations of int and bits/bit in MHS and RHS. - As there may be illegal assignments from integer value to bit, says assign 2 to a bit, but we only check this during instantiation in some cases, e.g. bit V = !if(!eq(x, 17), 0, 2); Verbose diagnostic message is generated when invalid value is resolveed to help locating the error. - PR8330 is fixed as well. llvm-svn: 163360
* Remove unused variable introduced by r163346.David Blaikie2012-09-061-2/+0
| | | | llvm-svn: 163359
* Don't include stdint.h directly.Eli Friedman2012-09-061-1/+1
| | | | llvm-svn: 163354
* Explicitly erase the file from disk if something bad happened. ↵Bill Wendling2012-09-061-1/+5
| | | | | | <rdar://problem/12184899> llvm-svn: 163349
* The Mips standalone assembler memory instruction support.Jack Carter2012-09-062-7/+252
| | | | | | | | | This includes sb,sc,sh,sw,lb,lw,lbu,lh,lhu,ll,lw Test case included Contributer: Vladimir Medic llvm-svn: 163346
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-0622-0/+60
| | | | | | No functional change. llvm-svn: 163344
* TiedTo is an integer, not a bool.Jakob Stoklund Olesen2012-09-061-2/+2
| | | | | | Thanks, Andy. llvm-svn: 163343
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-0620-0/+54
| | | | | | No functional change. llvm-svn: 163339
* Allow overlaps between virtreg and physreg live ranges.Jakob Stoklund Olesen2012-09-067-14/+70
| | | | | | | | | | | | | | | | | The RegisterCoalescer understands overlapping live ranges where one register is defined as a copy of the other. With this change, register allocators using LiveRegMatrix can do the same, at least for copies between physical and virtual registers. When a physreg is defined by a copy from a virtreg, allow those live ranges to overlap: %CL<def> = COPY %vreg11:sub_8bit; GR32_ABCD:%vreg11 %vreg13<def,tied1> = SAR32rCL %vreg13<tied0>, %CL<imp-use,kill> We can assign %vreg11 to %ECX, overlapping the live range of %CL. llvm-svn: 163336
* Handle overlapping regunit intervals in LiveIntervals::addKillFlags().Jakob Stoklund Olesen2012-09-063-4/+46
| | | | | | | | | | | | | | | | | | We will soon allow virtual register live ranges to overlap regunit live ranges when the physreg is defined as a copy of the virtreg: %EAX = COPY %vreg5 FOO %vreg5 BAR %EAX<kill> There is no real interference since %vreg5 and %EAX have the same value where they overlap. This patch prevents addKillFlags from adding virtreg kill flags to FOO where the assigned physreg is overlapping the virtual register live range. llvm-svn: 163335
* Clear kill flags while computing live ranges.Jakob Stoklund Olesen2012-09-061-1/+5
| | | | | | | | | Kill flags are difficult to maintain, and liveness queries are better handled by live intervals. Kill flags are reinserted after register allocation by addKillFlags(). llvm-svn: 163334
* Dont cast away const needlessly. Found by gcc48 -Wcast-qual.Roman Divacky2012-09-063-3/+4
| | | | llvm-svn: 163324
* Diagnose invalid alignments on duplicating VLDn instructions.Tim Northover2012-09-063-2/+10
| | | | | | Patch by Chris Lidbury. llvm-svn: 163323
* Check for invalid alignment values when decoding VLDn/VSTn (single ln) ↵Tim Northover2012-09-066-8/+131
| | | | | | | | instructions. Patch by Chris Lidbury. llvm-svn: 163321
* BasicAA: Recognize cyclic NoAlias phisArnold Schwaighofer2012-09-062-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enhances basic alias analysis to recognize phis whose first incoming values are NoAlias and whose other incoming values are just the phi node itself through some amount of recursion. Example: With this change basicaa reports that ptr_phi and ptr_phi2 do not alias each other. bb: ptr = ptr2 + 1 loop: ptr_phi = phi [bb, ptr], [loop, ptr_plus_one] ptr2_phi = phi [bb, ptr2], [loop, ptr2_plus_one] ... ptr_plus_one = gep ptr_phi, 1 ptr2_plus_one = gep ptr2_phi, 1 This enables the elimination of one load in code like the following: extern int foo; int test_noalias(int *ptr, int num, int* coeff) { int *ptr2 = ptr; int result = (*ptr++) * (*coeff--); while (num--) { *ptr2++ = *ptr; result += (*coeff--) * (*ptr++); } *ptr = foo; return result; } Part 2/2 of fix for PR13564. llvm-svn: 163319
* Use correct part of complex operand to encode VST1 alignment.Tim Northover2012-09-062-2/+79
| | | | | | Patch by Chris Lidbury. llvm-svn: 163318
* BasicAA: GEPs of NoAlias'ing base ptr with equivalent indices are NoAliasArnold Schwaighofer2012-09-062-9/+119
| | | | | | | | | | | | If we can show that the base pointers of two GEPs don't alias each other using precise analysis and the indices and base offset are equal then the two GEPs also don't alias each other. This is primarily needed for the follow up patch that analyses NoAlias'ing PHI nodes. Part 1/2 of fix for PR13564. llvm-svn: 163317
* Disable stack coloring by default in order to resolve the i386 failures.Nadav Rotem2012-09-062-3/+3
| | | | llvm-svn: 163316
* Tablegen: Add OperandWithDefaultOps Operand typeTom Stellard2012-09-065-56/+53
| | | | | | | This Operand type takes a default argument, and is initialized to this value if it does not appear in a patter. llvm-svn: 163315
* AVX2 optimization.Elena Demikhovsky2012-09-062-0/+51
| | | | | | Added generation of VPSHUB instruction for <32 x i8> vector shuffle when possible. llvm-svn: 163312
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