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* Clean this up slightly, doesn't really fall through.Eric Christopher2012-08-291-2/+1
| | | | llvm-svn: 162848
* Refactor setExecutionDomain to be clearer about what it's doing and more robust.Tim Northover2012-08-291-45/+53
| | | | llvm-svn: 162844
* Make helper function static.Benjamin Kramer2012-08-291-1/+1
| | | | llvm-svn: 162843
* Make MemoryBuiltins aware of TargetLibraryInfo.Benjamin Kramer2012-08-2931-184/+361
| | | | | | | | | | | | | | | | This disables malloc-specific optimization when -fno-builtin (or -ffreestanding) is specified. This has been a problem for a long time but became more severe with the recent memory builtin improvements. Since the memory builtin functions are used everywhere, this required passing TLI in many places. This means that functions that now have an optional TLI argument, like RecursivelyDeleteTriviallyDeadFunctions, won't remove dead mallocs anymore if the TLI argument is missing. I've updated most passes to do the right thing. Fixes PR13694 and probably others. llvm-svn: 162841
* Convert FMA4 patterns to use target specific nodes instead of intrinsics to ↵Craig Topper2012-08-293-38/+36
| | | | | | align with FMA3. llvm-svn: 162829
* Make use of the LLVM_DELETED_FUNCTION macro.Craig Topper2012-08-2917-35/+43
| | | | llvm-svn: 162828
* Add virtual keywords for methods that override the base class.Craig Topper2012-08-291-8/+8
| | | | llvm-svn: 162826
* Cleanup sloppy code. Jakob's review.Andrew Trick2012-08-291-4/+3
| | | | llvm-svn: 162825
* Fix a nondeterminism in the ARM assembler.Andrew Trick2012-08-291-0/+9
| | | | | | | | | | Adding arbitrary records to ARM.td would break basic-arm-instructions.s because selection of nop vs mov r0,r0 was ambiguous (this will be tested by a subsequent addition to ARM.td). An imperfect but sensible fix is to give precedence to match rules that have more constraints. llvm-svn: 162824
* [arm-fast-isel] Add support for ARM PIC.Jush Lu2012-08-292-6/+59
| | | | llvm-svn: 162823
* Fix ARM vector copies of overlapping register tuples.Andrew Trick2012-08-291-0/+13
| | | | | | | | I have tested the fix, but have not been successfull in generating a robust unit test. This can only be exposed through particular register assignments. llvm-svn: 162821
* cleanupAndrew Trick2012-08-291-21/+19
| | | | llvm-svn: 162820
* Create llvm/test/Object/Mips/lit.local.cfg to check Mips in targets_to_build.NAKAMURA Takumi2012-08-291-0/+5
| | | | llvm-svn: 162819
* Verify the tied operand flags.Jakob Stoklund Olesen2012-08-291-0/+37
| | | | | | | | WHen running with -verify-machineinstrs, check that tied operands come in matching use/def pairs, and that they are consistent with MCInstrDesc when it applies. llvm-svn: 162816
* Enable recursing into the compiler-rt projcet with the CMake build.Chandler Carruth2012-08-291-0/+8
| | | | | | | | | | | | | This only fires if using a recent enough CMake -- compiler-rt uses a few of the more advanced features that not everyone needs. Please let me know if anyone sees issues with this. I'll be updating documentation and other stuff to tell people about this. Many thanks to Alexey for doing a ton of work to get ASan's CMake build into a really fantastic shape. =] llvm-svn: 162815
* Maintain a vaild isTied bit as operands are added and removed.Jakob Stoklund Olesen2012-08-292-1/+51
| | | | | | | | The isTied bit is set automatically when a tied use is added and MCInstrDesc indicates a tied operand. The tie is broken when one of the tied operands is removed. llvm-svn: 162814
* llvm/test: [CMake] Add profile_rt-shared to deps.NAKAMURA Takumi2012-08-291-0/+1
| | | | llvm-svn: 162813
* libprofile: [CMake] Let libprofile_rt be not loadable_module but shared ↵NAKAMURA Takumi2012-08-291-1/+2
| | | | | | library. Autoconf's one does so. llvm-svn: 162812
* llvm/test/Analysis/Profiling: Mark 3 of them as REQUIRES: loadable_module.NAKAMURA Takumi2012-08-293-0/+9
| | | | | FIXME: profile_rt.dll could be built on win32. llvm-svn: 162811
* Moved input for objdump test from Mips to Inputs.Jack Carter2012-08-292-1/+1
| | | | llvm-svn: 162808
* Typo.Chad Rosier2012-08-281-1/+1
| | | | llvm-svn: 162807
* Add comments on the literal value used.Michael Liao2012-08-281-1/+1
| | | | llvm-svn: 162805
* LLI: move instruction cache tweaks.Jim Grosbach2012-08-281-4/+4
| | | | | | | | Invalidate the instruction cache right before we start actually executing code, otherwise we can miss some that came later. This is still not quite right for a truly lazilly compiled environment, but it's closer. llvm-svn: 162803
* Profile: set branch weight metadata with data generated from profiling.Manman Ren2012-08-2812-26/+1001
| | | | | | | | | This patch implements ProfileDataLoader which loads profile data generated by -insert-edge-profiling and updates branch weight metadata accordingly. Patch by Alastair Murray. llvm-svn: 162799
* The instruction DEXT may be transformed into DEXTU or DEXTM dependingJack Carter2012-08-285-3/+82
| | | | | | | | | | | | | | | | | | | | | on the size of the extraction and its position in the 64 bit word. This patch allows support of the dext transformations with mips64 direct object output. 0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32 DINS The field is entirely contained in the right-most word of the doubleword 32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64 DINSM The field straddles the words of the doubleword 32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32 DINSU The field is entirely contained in the left-most word of the doubleword llvm-svn: 162782
* Some of the instructions in the Mips instruction set are revisionJack Carter2012-08-283-1/+27
| | | | | | | | | | | | delimited. llvm-mc -disassemble access these through the -mattr option. llvm-objdump -disassemble had no such way to set the attribute so some instructions were just not recognized for disassembly. This patch accepts llvm-mc mechanism for specifying the attributes. llvm-svn: 162781
* Explicitly update the number of nodes to be traversedMichael Liao2012-08-281-1/+1
| | | | llvm-svn: 162780
* Some instructions are passed to the assembler to beJack Carter2012-08-282-21/+28
| | | | | | | | | | | | | transformed to the final instruction variant. An example would be dsrll which is transformed into dsll32 if the shift value is greater than 32. For direct object output we need to do this transformation in the codegen. If the instruction was inside branch delay slot, it was being missed. This patch corrects this oversight. llvm-svn: 162779
* Emit word of zeroes after the last instruction as a start of the mandatoryRoman Divacky2012-08-282-0/+25
| | | | | | | | | | traceback table on PowerPC64. This helps gdb handle exceptions. The other mandatory fields are ignored by gdb and harder to implement so just add there a FIXME. Patch by Bill Schmidt. PR13641. llvm-svn: 162778
* Follow-up patch to r162731.Akira Hatanaka2012-08-281-8/+9
| | | | | | | | Fix a couple of bugs in mips' long branch pass. This patch was supposed to be committed along with r162731, so I don't have a new test case. llvm-svn: 162777
* Add a MachineOperand::isTied() flag.Jakob Stoklund Olesen2012-08-282-21/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While in SSA form, a MachineInstr can have pairs of tied defs and uses. The tied operands are used to represent read-modify-write operands that must be assigned the same physical register. Previously, tied operand pairs were computed from fixed MCInstrDesc fields, or by using black magic on inline assembly instructions. The isTied flag makes it possible to add tied operands to any instruction while getting rid of (some of) the inlineasm magic. Tied operands on normal instructions are needed to represent predicated individual instructions in SSA form. An extra <tied,imp-use> operand is required to represent the output value when the instruction predicate is false. Adding a predicate to: %vreg0<def> = ADD %vreg1, %vreg2 Will look like: %vreg0<tied,def> = ADD %vreg1, %vreg2, pred:3, %vreg7<tied,imp-use> The virtual register %vreg7 is the value given to %vreg0 when the predicate is false. It will be assigned the same physreg as %vreg0. This commit adds the isTied flag and sets it based on MCInstrDesc when building an instruction. The flag is not used for anything yet. llvm-svn: 162774
* Don't allow TargetFlags on MO_Register MachineOperands.Jakob Stoklund Olesen2012-08-282-10/+21
| | | | | | | | | | | | Register operands are manipulated by a lot of target-independent code, and it is not always possible to preserve target flags. That means it is not safe to use target flags on register operands. None of the targets in the tree are using register operand target flags. External targets should be using immediate operands to annotate instructions with operand modifiers. llvm-svn: 162770
* Patch by Sean Silva to un-barf his computer by explicitly removing the '\n'Bill Wendling2012-08-281-3/+2
| | | | | | character instead of always the last character. llvm-svn: 162767
* Add PPC Freescale e500mc and e5500 subtargets.Hal Finkel2012-08-2810-2/+653
| | | | | | | | | Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to the PowerPC backend. Patch by Tobias von Koch. llvm-svn: 162764
* InstCombine: Defensively avoid undefined shifts by limiting the amount to ↵Benjamin Kramer2012-08-281-2/+2
| | | | | | | | | the bit width. No test case, undefined shifts get folded early, but can occur when other transforms generate a constant. Thanks to Duncan for bringing this up. llvm-svn: 162755
* InstCombine: Guard the transform introduced in r162743 against large ints ↵Benjamin Kramer2012-08-282-12/+37
| | | | | | and non-const shifts. llvm-svn: 162751
* Make sure that we don't call getZExtValue on values > 64 bits.Nadav Rotem2012-08-282-8/+15
| | | | | | Thanks Benjamin for noticing this. llvm-svn: 162749
* Teach InstCombine to canonicalize [SU]div+[AL]shl patterns.Nadav Rotem2012-08-283-2/+72
| | | | | | | | | | For example: %1 = lshr i32 %x, 2 %2 = udiv i32 %1, 100 rdar://12182093 llvm-svn: 162743
* The commutative flag is already correctly set within the multiclass. If we setBill Wendling2012-08-282-1/+21
| | | | | | | | it here, then a 'register-memory' version would wrongly get the commutative flag. <rdar://problem/12180135> llvm-svn: 162741
* Convert V_SETALLONES/AVX_SETALLONES/AVX2_SETALLONES to Post-RA pseudos.Craig Topper2012-08-283-18/+10
| | | | llvm-svn: 162740
* Merge AVX_SET0PSY/AVX_SET0PDY/AVX2_SET0 into a single post-RA pseudo.Craig Topper2012-08-284-32/+19
| | | | llvm-svn: 162738
* llvm/test/CodeGen/X86/pr12312.ll: Add -mtriple=x86_64-unknown-unknown.NAKAMURA Takumi2012-08-281-2/+2
| | | | llvm-svn: 162736
* Fix PR12312Michael Liao2012-08-282-10/+160
| | | | | | | | | | - Add a target-specific DAG optimization to recognize a pattern PTEST-able. Such a pattern is a OR'd tree with X86ISD::OR as the root node. When X86ISD::OR node has only its flag result being used as a boolean value and all its leaves are extracted from the same vector, it could be folded into an X86ISD::PTEST node. llvm-svn: 162735
* Check all patterns for missing instruction flags.Jakob Stoklund Olesen2012-08-282-0/+72
| | | | | | | Both single-instruction and multi-instruction patterns can be checked for missing mayLoad / mayStore, and hasSideEffects flags. llvm-svn: 162734
* Remove extra MayLoad/MayStore flags from atomic_load/store.Jakob Stoklund Olesen2012-08-285-31/+25
| | | | | | | | | | | | | | | These extra flags are not required to properly order the atomic load/store instructions. SelectionDAGBuilder chains atomics as if they were volatile, and SelectionDAG::getAtomic() sets the isVolatile bit on the memory operands of all atomic operations. The volatile bit is enough to order atomic loads and stores during and after SelectionDAG. This means we set mayLoad on atomic_load, mayStore on atomic_store, and mayLoad+mayStore on the remaining atomic read-modify-write operations. llvm-svn: 162733
* Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ↵Jakob Stoklund Olesen2012-08-286-169/+43
| | | | | | | | | | | ARM." This wasn't the right way to enforce ordering of atomics. We are already setting the isVolatile bit on memory operands of atomic operations which is good enough to enforce the correct ordering. llvm-svn: 162732
* Fix mips' long branch pass.Akira Hatanaka2012-08-283-109/+141
| | | | | | | | Instructions emitted to compute branch offsets now use immediate operands instead of symbolic labels. This change was needed because there were problems when R_MIPS_HI16/LO16 relocations were used to make shared objects. llvm-svn: 162731
* Split several PPC instruction classes.Hal Finkel2012-08-289-102/+269
| | | | | | | | | | | | | Slight reorganisation of PPC instruction classes for scheduling. No functionality change for existing subtargets. - Clearly separate load/store-with-update instructions from regular loads and stores. - Split IntRotateD -> IntRotateD and IntRotateDI - Split out fsub and fadd from FPGeneral -> FPAddSub - Update existing itineraries Patch by Tobias von Koch. llvm-svn: 162729
* Fix bug 13532.Akira Hatanaka2012-08-282-1/+13
| | | | | | | | | In SelectionDAGLegalize::ExpandLegalINT_TO_FP, expand INT_TO_FP nodes without using any f64 operations if f64 is not a legal type. Patch by Stefan Kristiansson. llvm-svn: 162728
* Allow remat of LI on PPC.Hal Finkel2012-08-284-3/+21
| | | | | | | | | | | Allow load-immediates to be rematerialised in the register coalescer for PPC. This makes test/CodeGen/PowerPC/big-endian-formal-args.ll fail, because it relies on a register move getting emitted. The immediate load is equivalent, so change this test case. Patch by Tobias von Koch. llvm-svn: 162727
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