summaryrefslogtreecommitdiffstats
path: root/llvm
Commit message (Collapse)AuthorAgeFilesLines
...
* Remove IIC_DEFAULT from X86Schedule.tdJakob Stoklund Olesen2013-03-255-78/+76
| | | | | | | | All the instructions tagged with IIC_DEFAULT had nothing in common, and we already have a NoItineraries class to represent untagged instructions. llvm-svn: 177937
* Annotate X86InstrCompiler.td with SchedRW lists.Jakob Stoklund Olesen2013-03-251-10/+20
| | | | llvm-svn: 177936
* Annotate shifts and rotates with SchedRW lists.Jakob Stoklund Olesen2013-03-251-17/+37
| | | | llvm-svn: 177935
* Disable some unsafe-fp-math DAG-combine transformation after legalization.Shuxin Yang2013-03-252-5/+31
| | | | | | | | | | | | | | For instance, following transformation will be disabled: x + x + x => 3.0f * x; The problem of these transformations is that it introduces a FP constant, which following Instruction-Selection pass cannot handle. Reviewed by Nadav, thanks a lot! rdar://13445387 llvm-svn: 177933
* Add an optimizer-side test case for ARC bug <rdar://13195034>, fixedJohn McCall2013-03-251-0/+63
| | | | | | in the frontend with @clang.arc.use. llvm-svn: 177928
* Couple more sets of tidying.Eric Christopher2013-03-251-5/+5
| | | | llvm-svn: 177920
* Disable profiling tests for Hexagon since it doesn't support JIT.Jyotsna Verma2013-03-251-0/+3
| | | | llvm-svn: 177917
* llvm/test/CodeGen/X86/atomic{32|64}.ll: Unmark them out of XFAIL:win32.NAKAMURA Takumi2013-03-252-2/+2
| | | | | | | I know it is incorrect and they'd fail with +Asserts for win32 targets, though. I'll try to fix them tonight. llvm-svn: 177914
* XFAIL some of the generic CodeGen tests for Hexagon.Jyotsna Verma2013-03-254-3/+4
| | | | | | | | | | | | test/CodeGen/Generic/2008-02-20-MatchingMem.ll: Test contains inline assembly not supported by Hexagon. Following tests are XFAILed due to multiple return values which Hexagon doesn't support. test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll test/CodeGen/Generic/select-cc.ll test/CodeGen/Generic/vector.ll llvm-svn: 177912
* X86DisassemblerDecoder.c: Make this C89-compliant.NAKAMURA Takumi2013-03-251-1/+1
| | | | llvm-svn: 177910
* Whitespace.NAKAMURA Takumi2013-03-251-160/+160
| | | | llvm-svn: 177909
* Fix a bug in fast-math fadd/fsub simplification. Shuxin Yang2013-03-252-10/+53
| | | | | | | | | | | The problem is that the code mistakenly took for granted that following constructor is able to create an APFloat from a *SIGNED* integer: APFloat::APFloat(const fltSemantics &ourSemantics, integerPart value) rdar://13486998 llvm-svn: 177906
* [ELF] dont compute symbolname size in every loopShankar Easwaran2013-03-251-1/+1
| | | | llvm-svn: 177903
* XFAIL DebugInfo tests for Hexagon.Jyotsna Verma2013-03-253-1/+3
| | | | | | | | | | | Hexagon does not support -filetype=obj(direct object generation) flag. Therefore, the following tests are being XFAILed: test/DebugInfo/dwarf-public-names.ll test/DebugInfo/member-pointers.ll test/DebugInfo/two-cus-from-same-file.ll llvm-svn: 177901
* Fix comment.Akira Hatanaka2013-03-251-3/+3
| | | | llvm-svn: 177899
* Formatting.Eric Christopher2013-03-251-4/+4
| | | | llvm-svn: 177898
* Disable Execution Engine tests not supported by Hexagon.Jyotsna Verma2013-03-251-0/+2
| | | | llvm-svn: 177896
* reflect comment to the official referenceShankar Easwaran2013-03-251-1/+1
| | | | llvm-svn: 177895
* Disable, for now, llvm/test/Transforms/GCOVProfiling on win32. I'll ↵NAKAMURA Takumi2013-03-252-0/+4
| | | | | | investigate them later. llvm-svn: 177894
* Use direct types in PowerPC instruction patterns.Ulrich Weigand2013-03-252-270/+262
| | | | | | | | | | This commit updates the PowerPC back-end (PPCInstrInfo.td and PPCInstr64Bit.td) to use types instead of register classes in instruction patterns, along the lines of Jakob Stoklund Olesen's changes in r177835 for Sparc. llvm-svn: 177890
* Use direct types in PowerPC Pat patterns.Ulrich Weigand2013-03-252-113/+113
| | | | | | | | | This commit updates the PowerPC back-end (PPCInstrInfo.td and PPCInstr64Bit.td) to use types instead of register classes in Pat patterns, along the lines of Jakob Stoklund Olesen's changes in r177829 for Sparc. llvm-svn: 177889
* x86 -- add the XTEST instructionDave Zarzycki2013-03-256-39/+43
| | | | llvm-svn: 177888
* x86 -- disassemble the REP/REPNE prefix when neededDave Zarzycki2013-03-252-7/+35
| | | | | | This fixes Apple bug: 13493622 llvm-svn: 177887
* Remove unnecessary attributes from test case.Chad Rosier2013-03-251-3/+1
| | | | llvm-svn: 177882
* Remove assert. There may be target-dependent attributes left.Bill Wendling2013-03-251-1/+0
| | | | llvm-svn: 177878
* Documentation: Replace dead link for binfmt_miscDmitri Gribenko2013-03-251-1/+1
| | | | | | Patch by Thomas Schwinge. llvm-svn: 177876
* [arm load/store optimizer] When trying to merge a base update load/store, makeChad Rosier2013-03-251-1/+1
| | | | | | | | | | | sure the base register and would-be writeback register don't conflict for stores. This was already being done for loads. Unfortunately, it is rather difficult to create a test case for this issue. It was exposed in 450.soplex at LTO and requires unlucky register allocation. <rdar://13394908> llvm-svn: 177874
* [tools][llvm-readobj] print the name of the section when iterating the ↵Shankar Easwaran2013-03-253-41/+48
| | | | | | symbol table / dynamic symbol table llvm-svn: 177873
* [ELF] add elf_hash function to compute the hash value of a symbol in the ↵Shankar Easwaran2013-03-251-0/+15
| | | | | | dynamic symbol table llvm-svn: 177872
* Teach cmake about the new Erlang GC files.Duncan Sands2013-03-252-0/+2
| | | | llvm-svn: 177869
* Add a GC plugin for ErlangYiannis Tsiouris2013-03-256-0/+234
| | | | llvm-svn: 177867
* Don't use add_llvm_definitions for adding warning flags. It makes it too hardDuncan Sands2013-03-251-14/+20
| | | | | | | | | to have them appear in the right order. Instead append all warnings explicitly to the language flags. This was already the case for many warnings. Fixes the issue of -Wno-maybe-uninitialized not being effective because -Wall was being placed after it rather than before. llvm-svn: 177866
* Refine fenv.h handling: check if the desired macros exist, before usingJoerg Sonnenberger2013-03-255-2/+186
| | | | | | | it. NetBSD/ARM and TILE-Gx are examples for platforms that have an unusable fenv.h and this avoids the need for a blacklist. llvm-svn: 177865
* Address issues found by Duncan during post-commit review of r177856.Arnaud A. de Grandmaison2013-03-252-34/+21
| | | | llvm-svn: 177863
* InstCombine: simplify comparisons to zero of (shl %x, Cst) or (mul %x, Cst)Arnaud A. de Grandmaison2013-03-252-0/+225
| | | | | | | | This simplification happens at 2 places : - using the nsw attribute when the shl / mul is used by a sign test - when the shl / mul is compared for (in)equality to zero llvm-svn: 177856
* Changed isNullOrUndef => IsNullOrUndef and isNoopInstruction => ↵Michael Gottesman2013-03-253-14/+14
| | | | | | IsNoopInstruction so that all helper functions are named similarly in ObjCARC.h. llvm-svn: 177855
* Mention the new TableGen pattern format in the release notes.Jakob Stoklund Olesen2013-03-251-0/+6
| | | | | | Make threats about removing the old syntax. llvm-svn: 177848
* [NVPTX] Fix handling of vector argumentsJustin Holewinski2013-03-243-7/+83
| | | | llvm-svn: 177847
* Clean up Sparc patterns.Jakob Stoklund Olesen2013-03-241-5/+5
| | | | | | | The types of register variables no longer need to be specified in output patterns. llvm-svn: 177845
* Allow types to be omitted in output patterns.Jakob Stoklund Olesen2013-03-242-0/+16
| | | | | | | | | | This syntax is now preferred: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; There is no reason to repeat the types in the output pattern. llvm-svn: 177844
* Allow TableGen DAG arguments to be just a name.Jakob Stoklund Olesen2013-03-243-16/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | DAG arguments can optionally be named: (dag node, node:$name) With this change, the node is also optional: (dag node, node:$name, $name) The missing node is treated as an UnsetInit, so the above is equivalent to: (dag node, node:$name, ?:$name) This syntax is useful in output patterns where we currently require the types of variables to be repeated: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr i32:$b, i32:$c)>; This is preferable: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; llvm-svn: 177843
* GettingStarted: Add Git clone instructions for compiler-rt and test-suiteTobias Grosser2013-03-241-1/+18
| | | | | Contributed-by: Thomas Schwinge <thomas@codesourcery.com> llvm-svn: 177841
* Minor cleanups. No functionality change.Jakub Staszak2013-03-241-6/+7
| | | | llvm-svn: 177837
* Use dyn_cast instead of isa && cast.Jakub Staszak2013-03-241-8/+6
| | | | | | No functionality change. llvm-svn: 177836
* Give Sparc instruction patterns direct types instead of register classes.Jakob Stoklund Olesen2013-03-242-88/+75
| | | | | | | Also update the documentation since Sparc is the nicest backend, and used as an example in WritingAnLLVMBackend. llvm-svn: 177835
* Allow direct value types to be used in instruction 'set' patterns.Jakob Stoklund Olesen2013-03-241-2/+24
| | | | | | | | | | | | This makes it possible to define instruction patterns like this: def LDri : F3_2<3, 0b000000, (outs IntRegs:$dst), (ins MEMri:$addr), "ld [$addr], $dst", [(set i32:$dst, (load ADDRri:$addr))]>; ~~~ llvm-svn: 177834
* PPC ZERO register needs a register number of 0.Hal Finkel2013-03-231-0/+1
| | | | | | | | | In order for the new ZERO register to be used with MC, etc. we need to specify its register number (0). Thanks to Kai for reporting the problem! llvm-svn: 177833
* Note in PPCFunctionInfo VRSAVE spillsHal Finkel2013-03-234-14/+34
| | | | | | | | | | | | In preparation for using the new register scavenger capability for providing more than one register simultaneously, specifically note functions that have spilled VRSAVE (currently, this can happen only in functions that use the setjmp intrinsic). As with CR spilling, such functions will need to provide two emergency spill slots to the scavenger. No functionality change intended. llvm-svn: 177832
* MCize the bcl instruction in PPCAsmPrinterHal Finkel2013-03-231-4/+5
| | | | | | | | | I recently added a BCL instruction definition as part of implementing SjLj support. This can also be used to MCize bcl emission in the asm printer. No functionality change intended. llvm-svn: 177830
* Use direct types in Sparc def : Pat patterns.Jakob Stoklund Olesen2013-03-231-10/+10
| | | | | | | | | | The SelectionDAG graph has MVT type labels, not register classes, so this makes it clearer what is happening. This notation is also robust against adding more types to the IntRegs register class. llvm-svn: 177829
OpenPOWER on IntegriCloud