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* MC: Add target hook to control symbol quotingMatt Arsenault2015-06-0951-211/+317
| | | | llvm-svn: 239370
* Fix unused variable warningArnold Schwaighofer2015-06-091-0/+1
| | | | llvm-svn: 239369
* [NVPTX] run SROA after NVPTXFavorNonGenericAddrSpacesJingyue Wu2015-06-092-2/+8
| | | | | | | | | | | | | | | | | | Summary: This cleans up most allocas NVPTXLowerKernelArgs emits for byval parameters. Test Plan: makes bug21465.ll more stronger to verify no redundant local load/store. Reviewers: eliben, jholewinski Reviewed By: eliben, jholewinski Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D10322 llvm-svn: 239368
* MergeFunctions: Impose a total order on the replacement of functionsArnold Schwaighofer2015-06-093-5/+78
| | | | | | | | | | | | | We don't want to replace function A by Function B in one module and Function B by Function A in another module. If these functions are marked with linkonce_odr we would end up with a function stub calling B in one module and a function stub calling A in another module. If the linker decides to pick these two we will have two stubs calling each other. rdar://21265586 llvm-svn: 239367
* [WinEH] Cache declarations of frame intrinsicsReid Kleckner2015-06-081-6/+10
| | | | llvm-svn: 239361
* [MC] Use unsigned for the Kind bitfield in MCSymbolReid Kleckner2015-06-081-1/+3
| | | | | | | | | | | Fixes most of the test suite on Windows with clang-cl. I'm not sure why the test suite was passing with MSVC 2013. Maybe they changed their behavior and we are emulating their old sign extension behavior. I think this deserves more investigation, but I want to green the bot first. llvm-svn: 239357
* Fix clang-cl self-host -Wc++11-narrowing bugReid Kleckner2015-06-081-1/+1
| | | | | | | Use unsigned as the underlying storage type of the AMDGPU address space enum. llvm-svn: 239355
* [AArch64] AsmParser should be case insensitive about accepting vector ↵Ranjeet Singh2015-06-082-1/+9
| | | | | | | | register names. Differential Revision: http://reviews.llvm.org/D10320 llvm-svn: 239353
* [InstrInfo] Refactor foldOperandImpl to thread through InsertPt. NFCKeno Fischer2015-06-0813-104/+132
| | | | | | | | | | | | | | | | | | Summary: This was a longstanding FIXME and is a necessary precursor to cases where foldOperandImpl may have to create more than one instruction (e.g. to constrain a register class). This is the split out NFC changes from D6262. Reviewers: pete, ributzka, uweigand, mcrosier Reviewed By: mcrosier Subscribers: mcrosier, ted, llvm-commits Differential Revision: http://reviews.llvm.org/D10174 llvm-svn: 239336
* Fix a regression in .pop_section.Rafael Espindola2015-06-082-5/+30
| | | | | | | It was calling ChangeSection with the wrong current section, eventually leading to a crash. llvm-svn: 239335
* [X86][SSE] Added lzcnt vector tests.Simon Pilgrim2015-06-082-0/+3010
| | | | llvm-svn: 239333
* Include header file <functional>.Akira Hatanaka2015-06-081-0/+1
| | | | | | This is a follow-up to r239325. llvm-svn: 239329
* Prefer copy init over direct init. NFC.Benjamin Kramer2015-06-081-1/+1
| | | | llvm-svn: 239327
* [ARM] Pass a callback to FunctionPass constructors to enable skipping executionAkira Hatanaka2015-06-089-26/+97
| | | | | | | | | | | | | | | | on a per-function basis. Previously some of the passes were conditionally added to ARM's pass pipeline based on the target machine's subtarget. This patch makes changes to add those passes unconditionally and execute them conditonally based on the predicate functor passed to the pass constructors. This enables running different sets of passes for different functions in the module. rdar://problem/20542263 Differential Revision: http://reviews.llvm.org/D8717 llvm-svn: 239325
* Use a PointerUnion in MCSymbol for Section and Fragment. NFC.Pete Cooper2015-06-082-28/+20
| | | | | | | The Fragment and Section, and a bool for HasFragment were all used to create a PointerUnion. Just use a pointer union instead. llvm-svn: 239324
* Remove includes of MCMachOSymbolFlags.h after it was deletedPete Cooper2015-06-083-3/+0
| | | | llvm-svn: 239318
* Make flags get/set method protected so that all flags have to be managed by ↵Pete Cooper2015-06-081-11/+12
| | | | | | | | | | | subclasses. All of ELF, COFF and MachO now manipulate the flags in helpers so we don't need anyone to read the flags directly, but instead via those helpers. Reviewed by Rafael Espíndola. llvm-svn: 239317
* Move all flags logic to MCSymbolMachO.Pete Cooper2015-06-084-81/+119
| | | | | | | | | | | Also delete the now unused MCMachOSymbolFlags.h header as the only enum in there was moved to MCSymbolMachO. Similarly to ELF and COFF, manipulating the flags is now done via helpers instead of spread throughout the codebase. Reviewed by Rafael Espíndola. llvm-svn: 239316
* Add MCSymbolMachO which will be used to hide the MCSymbolMachO flags.Pete Cooper2015-06-082-1/+27
| | | | | | Reviewed by Rafael Espíndola. llvm-svn: 239315
* Move all of the MCSymbol COFF flags logic in to MCSymbolCOFF.Pete Cooper2015-06-084-18/+36
| | | | | | | | | All flags setting/getting is now done in the class with helper methods instead of users having to get the bits in the correct order. Reviewed by Rafael Espíndola. llvm-svn: 239314
* Move COFF Type in to the MCSymbolCOFF class.Pete Cooper2015-06-082-12/+12
| | | | | | | | | The flags field in MCSymbol only needs to be 16-bits on ELF and MachO. This moves the 16-bit Type out of there so that it can be reduced in size in a future commit. Reviewed by Rafael Espíndola. llvm-svn: 239313
* Add MCSymbolCOFF class and use it to get and set the COFF type field.Pete Cooper2015-06-084-10/+51
| | | | | | Reviewed by Rafael Espíndola. llvm-svn: 239312
* Change MCSymbol IsELF to an enum to support future MCSymbolCOFF and ↵Pete Cooper2015-06-083-6/+20
| | | | | | | | MCSymbolMachO. Reviewed by Rafael Espíndola. llvm-svn: 239311
* X86: Reject register operands with obvious type mismatches.Matthias Braun2015-06-082-0/+23
| | | | | | | | | | | | | While we have some code to transform specification like {ax} into {eax}/{rax} if the operand type isn't 16bit, we should reject cases where there is no sane way to do this, like the i128 type in the example. Related to rdar://21042280 Differential Revision: http://reviews.llvm.org/D10260 llvm-svn: 239309
* Fix assertion failure in global-merge with unused ConstantExprOliver Stannard2015-06-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The global-merge pass was crashing because it assumes that all ConstantExprs (reached via the global variables that they use) have at least one user. I haven't worked out a way to test this, as an unused ConstantExpr cannot be represented by serialised IR, and global-merge can only be run in llc, which does not run any passes which can make a ConstantExpr dead. This (reduced to the point of silliness) C code triggers this bug when compiled for arm-none-eabi at -O1: static a = 7; static volatile b[10] = {&a}; c; main() { c = 0; for (; c < 10;) printf(b[c]); } Differential Revision: http://reviews.llvm.org/D10314 llvm-svn: 239308
* [Hexagon] Adding functionality for searching for compound instruction pairs. ↵Colin LeMahieu2015-06-086-2/+457
| | | | | | Compound instructions reduce slot resource requirements freeing those packet slots up for more instructions. llvm-svn: 239307
* [DAGCombiner] Added CTLZ vector constant folding support.Simon Pilgrim2015-06-084-2/+214
| | | | llvm-svn: 239305
* fix typos; NFCSanjay Patel2015-06-081-4/+4
| | | | llvm-svn: 239303
* ARM]: Add support for MMFR4_EL1 in assemblerJaved Absar2015-06-085-0/+10
| | | | | | | This patch adds support for system register MMFR4_EL1 (memory model feature register) in the assembler. This register provides information about the implemented memory model and memory management support. llvm-svn: 239302
* [Mips64][mcjit] Add R_MIPS_PC32 relocationPetar Jovanovic2015-06-082-0/+14
| | | | | | | | | | This patch adds R_MIPS_PC32 relocation for Mips64. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D10235 llvm-svn: 239301
* AVX-512: Implemented 256/128bit VALIGND/Q instructions for SKX and KNLIgor Breger2015-06-087-39/+322
| | | | | | | | | Implemented DAG lowering for all these forms. Added tests for DAG lowering and encoding. Differential Revision: http://reviews.llvm.org/D10310 llvm-svn: 239300
* Minor refactoring of GEP handling in isDereferenceablePointerArtur Pilipenko2015-06-082-28/+28
| | | | | | | | | | For GEP instructions isDereferenceablePointer checks that all indices are constant and within bounds. Replace this index calculation logic to a call to accumulateConstantOffset. Separated from the http://reviews.llvm.org/D9791 Reviewed By: sanjoy Differential Revision: http://reviews.llvm.org/D9874 llvm-svn: 239299
* [LAA] Fix estimation of number of memchecksSilviu Baranga2015-06-083-43/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: We need to add a runtime memcheck for pair of accesses (x,y) where at least one of x and y are writes. Assuming we have w writes and r reads, currently this number is estimated as being w* (w+r-1). This estimation will count (write,write) pairs twice and will overestimate the number of checks required. This change adds a getNumberOfChecks method to RuntimePointerCheck, which will count the number of runtime checks needed (similar in implementation to needsAnyChecking) and uses it to produce the correct number of runtime checks. Test Plan: llvm test suite spec2k spec2k6 Performance results: no changes observed (not surprising since the formula for 1 writer is basically the same, which would covers most cases - at least with the current check limit). Reviewers: anemet Reviewed By: anemet Subscribers: mzolotukhin, llvm-commits Differential Revision: http://reviews.llvm.org/D10217 llvm-svn: 239295
* [DAGCombiner] Added CTTZ vector constant folding support.Simon Pilgrim2015-06-084-2/+192
| | | | llvm-svn: 239293
* [LoopVectorize] Teach Loop Vectorizor about interleaved memory accesses.Hao Liu2015-06-089-29/+1299
| | | | | | | | | | | | | | | | | | | | | | | | Interleaved memory accesses are grouped and vectorized into vector load/store and shufflevector. E.g. for (i = 0; i < N; i+=2) { a = A[i]; // load of even element b = A[i+1]; // load of odd element ... // operations on a, b, c, d A[i] = c; // store of even element A[i+1] = d; // store of odd element } The loads of even and odd elements are identified as an interleave load group, which will be transfered into vectorized IRs like: %wide.vec = load <8 x i32>, <8 x i32>* %ptr %vec.even = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %vec.odd = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> The stores of even and odd elements are identified as an interleave store group, which will be transfered into vectorized IRs like: %interleaved.vec = shufflevector <4 x i32> %vec.even, %vec.odd, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> store <8 x i32> %interleaved.vec, <8 x i32>* %ptr This optimization is currently disabled by defaut. To try it by adding '-enable-interleaved-mem-accesses=true'. llvm-svn: 239291
* [llvm-readobj] Use the new symbol API.Davide Italiano2015-06-081-7/+7
| | | | llvm-svn: 239286
* [LoopAccessAnalysis] Teach LAA to check the memory dependence between ↵Hao Liu2015-06-082-12/+641
| | | | | | | | strided accesses. Differential Revision: http://reviews.llvm.org/D9368 llvm-svn: 239285
* Do not build LLD from tools/Makefile, as LLD no longer has a Makefile build.Peter Collingbourne2015-06-081-2/+1
| | | | llvm-svn: 239283
* Remove SCEVCache and FindConstantPointers from complete loop unrolling ↵Michael Zolotukhin2015-06-081-212/+89
| | | | | | | | | | | | | | | | | | | | heuristic. Summary: Using some SCEV functionality helped to entirely remove SCEVCache class and FindConstantPointers SCEV visitor. Also, this makes the code more universal - I'll take advandate of it in next patches where I start handling additional types of instructions. Test Plan: Tests would be submitted in subsequent patches. Reviewers: atrick, chandlerc Reviewed By: atrick, chandlerc Subscribers: atrick, llvm-commits Differential Revision: http://reviews.llvm.org/D10205 llvm-svn: 239282
* Fix Windows build.Peter Collingbourne2015-06-081-0/+4
| | | | llvm-svn: 239279
* llvm-ar: Move archive writer to Object.Peter Collingbourne2015-06-084-326/+396
| | | | | | | | | No functional change intended, other than some minor changes to certain diagnostics. Differential Revision: http://reviews.llvm.org/D10296 llvm-svn: 239278
* [TableGen] Remove unnecessary default constructed SMLoc that just existed to ↵Craig Topper2015-06-081-5/+1
| | | | | | return. Instead just call the default constructor in the return. llvm-svn: 239277
* [TableGen] Use range-based for loop. NFCCraig Topper2015-06-081-3/+2
| | | | llvm-svn: 239276
* [TableGen] Remove unnecessary extern declaration that's already in an ↵Craig Topper2015-06-081-2/+0
| | | | | | included header file. llvm-svn: 239275
* [TableGen] Use the SMLoc header file instead of SourceMgr header file in a ↵Craig Topper2015-06-083-3/+6
| | | | | | couple places. NFC llvm-svn: 239274
* [objdump] Moving PrintImmHex out of MachODump and in to llvm-objdump and ↵Colin LeMahieu2015-06-074-4/+16
| | | | | | setting instprinter appropriately. llvm-svn: 239265
* [X86] Added tzcnt vector tests.Simon Pilgrim2015-06-072-0/+2795
| | | | llvm-svn: 239264
* [MC] Function naming NFC.Colin LeMahieu2015-06-071-2/+2
| | | | llvm-svn: 239263
* SeparateConstOffsetFromGEP: Pass address space to isLegalAddressingModeMatt Arsenault2015-06-073-1/+100
| | | | llvm-svn: 239262
* Make NaryReassociate pass the address space to isLegalAddressingModeMatt Arsenault2015-06-071-1/+3
| | | | | | | No test since the kinds of transforms this prevents seem to not really be relevant for SI's different addressing modes. llvm-svn: 239261
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