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* [tablegen][globalisel] Add support for nested instruction matching.Daniel Sanders2017-04-048-77/+408
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Lift the restrictions that prevented the tree walking introduced in the previous change and add support for patterns like: (G_ADD (G_MUL (G_SEXT $src1), (G_SEXT $src2)), $src3) -> SMADDWrrr $dst, $src1, $src2, $src3 Also adds support for G_SEXT and G_ZEXT to support these cases. One particular aspect of this that I should draw attention to is that I've tried to be overly conservative in determining the safety of matches that involve non-adjacent instructions and multiple basic blocks. This is intended to be used as a cheap initial check and we may add a more expensive check in the future. The current rules are: * Reject if any instruction may load/store (we'd need to check for intervening memory operations. * Reject if any instruction has implicit operands. * Reject if any instruction has unmodelled side-effects. See isObviouslySafeToFold(). Reviewers: t.p.northover, javed.absar, qcolombet, aditya_nandakumar, ab, rovka Reviewed By: ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30539 llvm-svn: 299430
* [mips] Deal with empty blocks in the mips hazard schedulerSimon Dardis2017-04-042-11/+106
| | | | | | | | | | | | This patch teaches the hazard scheduler how to handle empty blocks when search for the next real instruction when dealing with forbidden slots. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D31293 llvm-svn: 299427
* [X86] Add 64 bit pattern matching for PSADBWOren Ben Simhon2017-04-042-13/+388
| | | | | | | | | PSADBW pattern currently supports the 32 bit IR pattern and only GLT (greather than) comparison. The patch extends the pattern to catch also 64 bit IR pattern and includes all other comparison types (not only GLT). Differential Revision: https://reviews.llvm.org/D31577 llvm-svn: 299425
* Align all scalar numbers to LLVM_YAML_IS_FLOW_SEQUENCE_VECTORJonas Hahnfeld2017-04-0411-56/+21
| | | | | | | | | Otherwise, yamlize in YAMLTraits.h might be wrongly defined. This makes some AMDGPU tests fail when LLVM_LINK_LLVM_DYLIB is set. Differential Revision: https://reviews.llvm.org/D30508 llvm-svn: 299415
* [InstCombine] Use setAllBits in place of getAllOnesValue since we know the ↵Craig Topper2017-04-041-1/+1
| | | | | | bitwidths are the same. NFCI llvm-svn: 299413
* InstCombine: Use the InstSimplify hook for shufflevectorZvi Rackover2017-04-041-5/+4
| | | | | | | | | | | | | | Summary: Start using the recently added InstSimplify hook for shuffles in the respective InstCombine visitor. Reviewers: spatel, RKSimon, craig.topper, majnemer Reviewed By: majnemer Subscribers: majnemer, llvm-commits Differential Revision: https://reviews.llvm.org/D31526 llvm-svn: 299412
* [PDB] Save one type record copyReid Kleckner2017-04-043-21/+25
| | | | | | | | | | | | | | | | | | Summary: The TypeTableBuilder provides stable storage for type records. We don't need to copy all of the bytes into a flat vector before adding it to the TpiStreamBuilder. This makes addTypeRecord take an ArrayRef<uint8_t> and a hash code to go with it, which seems like a simplification. Reviewers: ruiu, zturner, inglorion Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31634 llvm-svn: 299406
* [codeview] Cope with unsorted streams in type mergingReid Kleckner2017-04-037-44/+175
| | | | | | | | | | | | | | | Summary: MASM can produce type streams that are not topologically sorted. It can even produce type streams with circular references, but those are not common in practice. Reviewers: inglorion, ruiu Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31629 llvm-svn: 299403
* [Fuzzer] Flush std::cout before aborting in CxxStringEqTestReid Kleckner2017-04-031-0/+1
| | | | | | | On Windows, abort() does not appear to flush std::cout. Should fix red sanitizer-windows bot. llvm-svn: 299398
* add/move codegen tests for and/or of setcc; NFCSanjay Patel2017-04-035-73/+173
| | | | llvm-svn: 299396
* Update stale doxygen links in ProgrammersManual.rstTim Northover2017-04-031-17/+17
| | | | | | Patch by Wei-Ren Chen. llvm-svn: 299395
* InstSimplify: Add a hook for shufflevectorZvi Rackover2017-04-034-6/+85
| | | | | | | | | | | | | | | | | | Summary: Add a hook for simplification of shufflevector's with the following rules: - Constant folding - NFC, as it was already being done by the default handler. - If only one of the operands is constant, constant fold the shuffle if the mask does not select elements from the variable operand - to show the hook is firing and affecting the test-cases. Reviewers: RKSimon, craig.topper, spatel, sanjoy, nlopes, majnemer Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31525 llvm-svn: 299393
* Reland r298901 with modifications (reverted in r298932)Weiming Zhao2017-04-0318-37/+180
| | | | | | | | | | | | | | | | | | | Dont emit Mapping symbols for sections that contain only data. Summary: Dont emit mapping symbols for sections that contain only data. Reviewers: rengolin, weimingz, kparzysz, t.p.northover, peter.smith Reviewed By: t.p.northover Patched by Shankar Easwaran <shankare@codeaurora.org> Subscribers: alekseyshl, t.p.northover, llvm-commits Differential Revision: https://reviews.llvm.org/D30724 llvm-svn: 299392
* AMDGPU: Remove llvm.SI.vs.load.inputMatt Arsenault2017-04-039-32/+20
| | | | llvm-svn: 299391
* DAG: Fix missing legalization for any_extend_vector_inreg operandsMatt Arsenault2017-04-033-0/+75
| | | | llvm-svn: 299389
* [codeview] Add support for label type recordsReid Kleckner2017-04-0310-1/+66
| | | | | | MASM can produce these type records. llvm-svn: 299388
* [X86][SSE]] Lower BUILD_VECTOR with repeated elts as BUILD_VECTOR + ↵Simon Pilgrim2017-04-0312-103/+142
| | | | | | | | | | | | | | | | VECTOR_SHUFFLE It can be costly to transfer from the gprs to the xmm registers and can prevent loads merging. This patch splits vXi16/vXi32/vXi64 BUILD_VECTORS that use the same operand in multiple elements into a BUILD_VECTOR with only a single insertion of each of those elements and then performs an unary shuffle to duplicate the values. There are a couple of minor regressions this patch unearths due to some missing MOVDDUP/BROADCAST folds that I will address in a future patch. Note: Now that vector shuffle lowering and combining is pretty good we should be reusing that instead of duplicating so much in LowerBUILD_VECTOR - this is the first of several patches to address this. Differential Revision: https://reviews.llvm.org/D31373 llvm-svn: 299387
* [InstCombine] Remove canonicalization for (X & C1) | C2 --> (X | C2) & ↵Craig Topper2017-04-031-11/+0
| | | | | | | | | | (C1|C2) when C1 & C2 have common bits. It turns out that SimplifyDemandedInstructionBits will get called earlier and remove bits from C1 first. Effectively doing (X & (C1&C2)) | C2. So by the time it got to this check there could be no common bits. I think the DAGCombiner has the same check but its check can be executed because it handles demanded bits later. I'll look at it next. llvm-svn: 299384
* x86 interrupt calling convention: re-align stack pointer on 64-bit if an ↵Amjad Aboud2017-04-034-10/+30
| | | | | | | | | | | | | | | | error code was pushed The x86_64 ABI requires that the stack is 16 byte aligned on function calls. Thus, the 8-byte error code, which is pushed by the CPU for certain exceptions, leads to a misaligned stack. This results in bugs such as Bug 26413, where misaligned movaps instructions are generated. This commit fixes the misalignment by adjusting the stack pointer in these cases. The adjustment is done at the beginning of the prologue generation by subtracting another 8 bytes from the stack pointer. These additional bytes are popped again in the function epilogue. Fixes Bug 26413 Patch by Philipp Oppermann. Differential Revision: https://reviews.llvm.org/D30049 llvm-svn: 299383
* [CodeGenPrep] move aarch64-type-promotion to CGPJun Bum Lim2017-04-039-58/+374
| | | | | | | | | | | | | | | | | Summary: Move the aarch64-type-promotion pass within the existing type promotion framework in CGP. This change also support forking sexts when a new sext is required for promotion. Note that change is based on D27853 and I am submitting this out early to provide a better idea on D27853. Reviewers: jmolloy, mcrosier, javed.absar, qcolombet Reviewed By: qcolombet Subscribers: llvm-commits, aemerson, rengolin, mcrosier Differential Revision: https://reviews.llvm.org/D28680 llvm-svn: 299379
* [DAGCombine][InstCombine] Fix inverted if condition in equivalent comments ↵Craig Topper2017-04-032-2/+2
| | | | | | in DAGCombine and InstCombine. NFC llvm-svn: 299378
* Fix LLVMBuild.txt typo. NFCJoel Jones2017-04-031-1/+1
| | | | llvm-svn: 299373
* AMDGPU: Remove legacy bfe intrinsicsMatt Arsenault2017-04-0310-1252/+159
| | | | llvm-svn: 299372
* [Support] Make printAllJSONValues public, for custom output.Graydon Hoare2017-04-031-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This changes the static method TimerGroup::printAllJSONValues from private to public, to match the static method TimerGroup::printAll. When trying to drive the reporting machinery by hand, the existing API is _almost_ flexible enough, but this entrypoint is required to intermix printing timers with other non-timer output. The underlying motive here is a Swift change to consolidate the collection of timers, LLVM statistics and other (non-assert-dependent) counters into JSON files, which requires a bit of manual intervention in LLVM's stat and timer output routines. See https://github.com/apple/swift/pull/8477 for details. Reviewers: MatzeB Reviewed By: MatzeB Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31566 llvm-svn: 299371
* Bitcode: Remove reader support for MODULE_CODE_PURGEVALS.Peter Collingbourne2017-04-034-21/+0
| | | | | | | | | | Support for writing this module code was removed in r73220, which was well before the LLVM 3.0 release, so we do not need to be able to understand it for backwards compatibility. Differential Revision: https://reviews.llvm.org/D31563 llvm-svn: 299370
* [InstCombine] Add test cases showing how we fail to fold vector constants ↵Craig Topper2017-04-033-0/+53
| | | | | | into selects the way we do with scalars. llvm-svn: 299369
* Revert "[DAGCombine] A shuffle of a splat is always the splat itself"Zvi Rackover2017-04-032-12/+10
| | | | | | | | | | This reverts commit r299047 which is incorrect because the simplification may result in incorrect propogation of undefs to users of the folded shuffle. Thanks to Andrea Di Biagio for pointing this out. llvm-svn: 299368
* [Hexagon] Factor out some common code in HexagonEarlyIfConv.cpp, NFCKrzysztof Parzyszek2017-04-031-12/+10
| | | | llvm-svn: 299367
* Revert r299337 "[InstCombine] Remove redundant combine from visitAnd"Craig Topper2017-04-032-0/+89
| | | | | | | | One of the tsan bots started failing at this commit. I don't see anything obviously wrong with the commit so trying this to see if it recovers. Failing log: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-autoconf/builds/6792 llvm-svn: 299366
* [InstCombine] fix formatting for foldLogOpOfMaskedICmps and related bits; NFCISanjay Patel2017-04-031-145/+158
| | | | | | | | | | | | 1. Improve enum, function, and variable names. 2. Improve comments. 3. Fix variable capitalization. 4. Run clang-format. As an existing code comment suggests, this should work with vector types / splat constants too, so making this look right first will reduce the diffs needed for that change. llvm-svn: 299365
* [APInt] Move isMask and isShiftedMask out of APIntOps and into the APInt ↵Craig Topper2017-04-038-43/+54
| | | | | | | | | | class. Implement them without memory allocation for multiword This moves the isMask and isShiftedMask functions to be class methods. They now use the MathExtras.h function for single word size and leading/trailing zeros/ones or countPopulation for the multiword size. The previous implementation made multiple temorary memory allocations to do the bitwise arithmetic operations to match the MathExtras.h implementation. Differential Revision: https://reviews.llvm.org/D31565 llvm-svn: 299362
* [DAGCombiner] Check limits before accessing array element (PR32502)Simon Pilgrim2017-04-031-1/+1
| | | | llvm-svn: 299361
* ARMAsmParser: clean up of isImmediate functionsSjoerd Meijer2017-04-0314-282/+193
| | | | | | | | | | | | | | | | | - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
* [InstCombine] Make foldOpWithConstantIntoOperand take a BinaryOperator ↵Craig Topper2017-04-032-2/+2
| | | | | | | | instead of a generic Instruction. It blindly assumes there are two operands so make it explicit. llvm-svn: 299351
* [InstCombine] Remove a And transform that should be handled by ↵Craig Topper2017-04-031-7/+0
| | | | | | SimplifyDemandedInstructionBits. NFCI llvm-svn: 299349
* Trailing whitespace.NAKAMURA Takumi2017-04-027-8/+8
| | | | llvm-svn: 299344
* Reformat.NAKAMURA Takumi2017-04-022-6/+6
| | | | llvm-svn: 299343
* [APInt] Make use of whichWord and maskBit to simplify some code. NFCCraig Topper2017-04-021-5/+3
| | | | llvm-svn: 299342
* [APInt] Add a public typedef for the internal type of APInt use it instead ↵Craig Topper2017-04-025-167/+169
| | | | | | | | | | | | | | | | of integerPart. Make APINT_BITS_PER_WORD and APINT_WORD_SIZE public. This patch is one step to attempt to unify the main APInt interface and the tc functions used by APFloat. This patch adds a WordType to APInt and uses that in all the tc functions. I've added temporary typedefs to APFloat to alias it to integerPart to keep the patch size down. I'll work on removing that in a future patch. In future patches I hope to reuse the tc functions to implement some of the main APInt functionality. I may remove APINT_ from BITS_PER_WORD and WORD_SIZE constants so that we don't have the repetitive APInt::APINT_ externally. Differential Revision: https://reviews.llvm.org/D31523 llvm-svn: 299341
* [InstCombine] Make InstCombiner::OptAndOp take a BinaryOperator instead of ↵Craig Topper2017-04-022-4/+4
| | | | | | | | | | an Instruction. The callers have already performed the necessary cast before calling. This allows us to remove a comment that says the instruction must be a BinaryOperator and make it explicit in the argument type. Had to add a default case to the switch because BinaryOperator::getOpcode() returns a BinaryOps enum. llvm-svn: 299339
* [X86][MMX] Improve support for folding fptosi from XMM to MMXSimon Pilgrim2017-04-022-7/+13
| | | | llvm-svn: 299338
* [InstCombine] Remove redundant combine from visitAndCraig Topper2017-04-022-89/+0
| | | | | | | | | | As far as I can tell this combine is fully handled by SimplifyDemandedInstructionBits. I was only looking at this because it is the only user of APIntOps::isShiftedMask which is itself broken. As demonstrated by r299187. I was going to fix isShiftedMask and needed to make sure we had coverage for the new cases it would expose to this combine. But looks like we can nuke it instead. Differential Revision: https://reviews.llvm.org/D31543 llvm-svn: 299337
* [X86][MMX] Simplify tablegen patterns by always combining MOVDQ2Q from v2i64Simon Pilgrim2017-04-022-5/+4
| | | | llvm-svn: 299336
* [X86][MMX] Added support for subvector extraction to MMX registerSimon Pilgrim2017-04-022-7/+7
| | | | llvm-svn: 299335
* APInt.h: Prune \param(s) in \returns. [-Wdocumentation]NAKAMURA Takumi2017-04-021-1/+1
| | | | llvm-svn: 299334
* Regenerate test with codegen. NFCI.Simon Pilgrim2017-04-021-4/+10
| | | | llvm-svn: 299333
* Regenerate test with codegen. NFCI.Simon Pilgrim2017-04-021-4/+89
| | | | llvm-svn: 299332
* Regenerate test. NFCI.Simon Pilgrim2017-04-021-56/+56
| | | | llvm-svn: 299331
* NewGVN: Handle coercion of constant stores, loads, memory insts.Daniel Berlin2017-04-026-6/+152
| | | | | | | | | | | | | | | | | Summary: Depends on D30928. This adds support for coercion of stores and memory instructions that do not require insertion to process. Another few tests down. I added the relevant tests from rle.ll Reviewers: davide Subscribers: llvm-commits, Prazek Differential Revision: https://reviews.llvm.org/D30929 llvm-svn: 299330
* [BypassSlowDivision] Do not bypass division of hash-like valuesNikolai Bozhenov2017-04-022-12/+202
| | | | | | | | | | | | | | | | | Disable bypassing if one of the operands looks like a hash value. Slow division often occurs in hashtable implementations and fast division is never taken there because a hash value is extremely unlikely to have enough upper bits set to zero. A value is considered to be hash-like if it is produced by 1) XOR operation 2) Multiplication by a constant wider than the shorter type 3) PHI node with all incoming values being hash-like Differential Revision: https://reviews.llvm.org/D28200 llvm-svn: 299329
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