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* llvm/test/CodeGen/X86/pr5145.ll: Tweak expressions to match for darwin target.NAKAMURA Takumi2012-09-211-8/+8
| | | | | | | .LBB0_1: # Linux LBB0_1: # Darwin llvm-svn: 164362
* Cortex-A9 latency fixes (w/ -schedmodel only).Andrew Trick2012-09-211-5/+5
| | | | | | Quick review against the manual revealed a few obvious mistakes. llvm-svn: 164361
* Add missing i8 max/min/umax/umin supportMichael Liao2012-09-213-10/+79
| | | | | | - Fix PR5145 and turn on test 8-bit atomic ops llvm-svn: 164358
* Revise td of X86 atomic instructionsMichael Liao2012-09-213-218/+209
| | | | | | | - Rewirte most atomic instructions in templates for both better maintenance and future extensions, such as HLE in TSX. llvm-svn: 164357
* docs: Fix Sphinx warning over Atomics.rst.Sean Silva2012-09-211-0/+5
| | | | | | | | Atomics.rst was not linked into the toctree. Docs now build warning-free! llvm-svn: 164356
* docs: Fix Sphinx warning over yaml2obj.rst.Sean Silva2012-09-211-0/+1
| | | | | | | | yaml2obj.rst was not included in the toctree Input from Michael Spencer. llvm-svn: 164355
* Mips16FrameLowering.cpp: Remove unused TII introduced in r164349. ↵NAKAMURA Takumi2012-09-211-1/+0
| | | | | | [-Wunused-variable] llvm-svn: 164354
* llvm/test/CodeGen/ARM/fast-isel.ll: Fix possible typos, ↵NAKAMURA Takumi2012-09-211-2/+2
| | | | | | | | s/@unaligned_i16_store/@unaligned_i16_load/g. I guess this had apparently passed in +Asserts possibly due to verborsity. llvm-svn: 164350
* Properly save and restore RA and Mips16 callee save registers S0,S1Akira Hatanaka2012-09-213-6/+52
| | | | | | Patch by Reed Kotler. llvm-svn: 164349
* Testcase does not need to be this strict.Chad Rosier2012-09-211-1/+1
| | | | llvm-svn: 164347
* Add newline.Chad Rosier2012-09-211-1/+1
| | | | llvm-svn: 164346
* [fast-isel] Fallback to SelectionDAG isel if we require strict alignment forChad Rosier2012-09-212-0/+36
| | | | | | | non-halfword-aligned i16 loads/stores. rdar://12304911 llvm-svn: 164345
* Tidy up. Whitespace.Jim Grosbach2012-09-211-2/+2
| | | | llvm-svn: 164344
* Tidy up. Formatting.Jim Grosbach2012-09-211-1/+1
| | | | llvm-svn: 164343
* ARM: Use a dedicated intrinsic for vector bitwise select.Jim Grosbach2012-09-213-2/+83
| | | | | | | | | | | The expression based expansion too often results in IR level optimizations splitting the intermediate values into separate basic blocks, preventing the formation of the VBSL instruction as the code author intended. In particular, LICM would often hoist part of the computation out of a loop. rdar://11011471 llvm-svn: 164340
* Ignore PHI-defs for -new-coalescer interference checks.Jakob Stoklund Olesen2012-09-202-4/+56
| | | | | | | | A PHI can't create interference on its own. If two live ranges interfere at a PHI, they must also interfere when leaving one of the PHI predecessors. llvm-svn: 164330
* Extend -new-coalescer SSA update to handle mapped values as well.Jakob Stoklund Olesen2012-09-202-9/+62
| | | | | | | | | | | | | The old-fashioned many-to-one value mapping doesn't always work when merging vector lanes. A value can map to multiple different values, and it can even be necessary to insert new PHIs. When a value number is defined by a copy from a value number that required SSa update, include the live range of the copied value number in the SSA update as well. It is not necessarily a copy of the original value number any longer. llvm-svn: 164329
* Only emit DW_AT_object_pointer if this is a definition.Eric Christopher2012-09-202-5/+2
| | | | llvm-svn: 164326
* SimplifyCFG: sink common codes from IF, ELSE blocks down to END block.Manman Ren2012-09-202-0/+226
| | | | | | | | | | | | We already have HoistThenElseCodeToIf, this patch implements SinkThenElseCodeToEnd. When END block has only two predecessors and each predecessor terminates with unconditional branches, we compare instructions in IF and ELSE blocks backwards and check whether we can sink the common instructions down. rdar://12191395 llvm-svn: 164325
* Try to make these tests more portable.Evan Cheng2012-09-203-7/+7
| | | | llvm-svn: 164320
* Fix broken check lines.Benjamin Kramer2012-09-201-3/+3
| | | | llvm-svn: 164317
* Fix function names in coding style examplesAndrew Trick2012-09-201-4/+4
| | | | llvm-svn: 164311
* Revert r164308 to fix buildbots.Bill Wendling2012-09-205-33/+30
| | | | llvm-svn: 164309
* Make the 'get*AlignmentFromAttr' functions into member functions within the ↵Bill Wendling2012-09-205-30/+33
| | | | | | Attributes class. llvm-svn: 164308
* Remove more bare uses of the different Attribute enums.Bill Wendling2012-09-202-16/+32
| | | | llvm-svn: 164307
* Specify cpu to get the correct instruction ordering. Remove XFAIL.Roman Divacky2012-09-201-6/+1
| | | | llvm-svn: 164306
* Make the 'getAsString' function a method of the Attributes class.Bill Wendling2012-09-204-54/+54
| | | | llvm-svn: 164305
* Fix 80-col violations.Nadav Rotem2012-09-201-13/+19
| | | | llvm-svn: 164297
* Make sure lli compiles all code before invalidating instruction caches.Tim Northover2012-09-201-0/+3
| | | | | | Patch from Amara Emerson. llvm-svn: 164296
* Change enum type in a static table to uint8_t instead. Saves about 700 ↵Craig Topper2012-09-201-6/+6
| | | | | | hundred bytes of static data. Change unsigned char in same table to uint8_t for explicitness. llvm-svn: 164285
* Specify CPu to prevent failure on ATOM due to different code schedulingMichael Liao2012-09-201-1/+1
| | | | llvm-svn: 164283
* Fix Sphinx warnings.Sean Silva2012-09-202-3/+4
| | | | | | Toctree was not being interlinked properly. llvm-svn: 164282
* Re-work X86 code generation of atomic ops with spin-loopMichael Liao2012-09-2013-553/+1709
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Rewrite/merge pseudo-atomic instruction emitters to address the following issue: * Reduce one unnecessary load in spin-loop previously the spin-loop looks like thisMBB: newMBB: ld t1 = [bitinstr.addr] op t2 = t1, [bitinstr.val] not t3 = t2 (if Invert) mov EAX = t1 lcs dest = [bitinstr.addr], t3 [EAX is implicit] bz newMBB fallthrough -->nextMBB the 'ld' at the beginning of newMBB should be lift out of the loop as lcs (or CMPXCHG on x86) will load the current memory value into EAX. This loop is refined as: thisMBB: EAX = LOAD [MI.addr] mainMBB: t1 = OP [MI.val], EAX LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined] JNE mainMBB sinkMBB: * Remove immopc as, so far, all pseudo-atomic instructions has all-register form only, there is no immedidate operand. * Remove unnecessary attributes/modifiers in pseudo-atomic instruction td * Fix issues in PR13458 - Add comprehensive tests on atomic ops on various data types. NOTE: Some of them are turned off due to missing functionality. - Revise tests due to the new spin-loop generated. llvm-svn: 164281
* Sphinxify DebuggingJITedCodeSean Silva2012-09-202-184/+147
| | | | | | LGTM by Michael Spencer llvm-svn: 164280
* Fix static function names in CodingStandards examples.Andrew Trick2012-09-201-6/+6
| | | | | | Try not to violate conventions immediately before explaining them. llvm-svn: 164278
* Convert some attribute existence queries over to use the predicate methods.Bill Wendling2012-09-194-38/+38
| | | | llvm-svn: 164268
* ARM: Tidy up IntrinsicsARM.td a bit.Jim Grosbach2012-09-191-225/+207
| | | | | | | Make the TargetPrefix setting one big setting instead of being spread out everywhere. No functional change. llvm-svn: 164265
* Add predicates for queries on whether an attribute exists.Bill Wendling2012-09-192-7/+87
| | | | llvm-svn: 164264
* Add in new data types that are used by AMDIL/ANL among others.Micah Villmow2012-09-195-64/+155
| | | | llvm-svn: 164261
* Soften the pattern-can-never-match error in TableGen into a warning. This ↵Owen Anderson2012-09-191-2/+5
| | | | | | pattern can be very useful in cases where you want to define a multiclass that covers both commutative and non-commutative operators (say, add and sub). llvm-svn: 164256
* Implement a correct copy constructor for Record. Now that we're using the ↵Owen Anderson2012-09-191-0/+8
| | | | | | | | ID number as a key in maps (for determinism), it is imperative that ID numbers be globally unique, even when we copy construct a Record. This fixes some obscure failure cases involving registers defined inside multiclasses or foreach constructs that would not receive a unique ID, and would end up being omitted from the AsmMatcher tables. llvm-svn: 164251
* Resolve conflicts involving dead vector lanes for -new-coalescer.Jakob Stoklund Olesen2012-09-192-9/+182
| | | | | | | | | | | | | | | | | | | | | A common coalescing conflict in vector code is lane insertion: %dst = FOO %src = BAR %dst:ssub0 = COPY %src The live range of %src interferes with the ssub0 lane of %dst, but that lane is never read after %src would have clobbered it. That makes it safe to merge the live ranges and eliminate the COPY: %dst = FOO %dst:ssub0 = BAR This patch teaches the new coalescer to resolve conflicts where dead vector lanes would be clobbered, at least as long as the clobbered vector lanes don't escape the basic block. llvm-svn: 164250
* This patch adds memory support functions which will later be used to ↵Andrew Kaylor2012-09-196-90/+747
| | | | | | implement section-specific protection handling in MCJIT. llvm-svn: 164249
* Add support for macro parameters/arguments delimited by spaces,Preston Gurd2012-09-196-33/+188
| | | | | | | | | | to improve compatibility with GNU as. Based on a patch by PaX Team. Fixed assertion failures on non-Darwin and added additional test cases. llvm-svn: 164248
* Add support for accessing an MDNode's operands via the C binding. Patch byDuncan Sands2012-09-192-0/+34
| | | | | | Anthony Bryant. llvm-svn: 164247
* Support default parameters/arguments for assembler macros.Preston Gurd2012-09-192-9/+41
| | | | | | | | This patch is based on the one by PaX Team. Patch by Andy Zhang! llvm-svn: 164246
* Enhance unmatched '.endr' directive error message in assembler.Preston Gurd2012-09-192-2/+2
| | | | | | | | The directive can be matched with directives other than '.rept' Patch by Andy Zhang! llvm-svn: 164245
* Unify the logic in SelectAtomicLoadAdd and SelectAtomicLoadArithMichael Liao2012-09-192-177/+142
| | | | | | | | | | | - Merge the processing of LOAD_ADD with other atomic load-arith operations - Separate the logic getting target constant for atomic-load-op and add an optimization for atomic-load-add on i16 with negative value - Optimize a minor case for atomic-fetch-add i16 with negative operand. Test case is revised. llvm-svn: 164243
* Renaming functions to match coding style guidelinesMichael Ilseman2012-09-191-4/+4
| | | | llvm-svn: 164238
* Really XFAIL test/CodeGen/PowerPC/structsinregs.ll.Jordan Rose2012-09-191-1/+1
| | | | | | | XFAIL needs a trailing colon. Hopefully this will get the buildbots happy again while Bill works on getting it passing. llvm-svn: 164237
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