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* [X86] Remove some redundant selection patterns.Craig Topper2016-05-012-11/+0
| | | | llvm-svn: 268180
* [AVX512] Replace vector_extract with extractelt in some patterns. They mean ↵Craig Topper2016-05-011-5/+5
| | | | | | the same thing but vector_extract is deprecated. NFC llvm-svn: 268179
* [SCEV] When printing via -analysis, dump loop dispositionSanjoy Das2016-05-012-0/+98
| | | | | | | | | | | There are currently some bugs in tree around SCEV caching an incorrect loop disposition. Printing out loop dispositions will let us write whitebox tests as those are fixed. The dispositions are printed as a list in "inside out" order, i.e. innermost loop first. llvm-svn: 268177
* Properly name LLVMSetIsInBounds's argument. NFCAmaury Sechet2016-05-012-3/+3
| | | | llvm-svn: 268176
* Capitalize align argument in the C API as per convention. NFCAmaury Sechet2016-05-011-2/+2
| | | | llvm-svn: 268175
* [AVX512] Add hasSideEffects/mayLoad/mayStore flags to some instructions.Craig Topper2016-05-011-4/+7
| | | | llvm-svn: 268174
* [ORC] Save AArch64 NEON state in the JIT reentry block.Lang Hames2016-05-012-43/+75
| | | | | | | The earlier version of the resolver code did not save NEON state, so it would have broken any callees that used floating point. llvm-svn: 268173
* [lit] Add %:[STpst] to represent paths without colons on Windows.Rui Ueyama2016-04-301-0/+18
| | | | | | | | | | | | Summary: We need these variables to concatenate two absolute paths to construct a valid path. Currently, %t\%t is, for example, expanded to C:\foo\C:\foo, which is not a valid path because ":" is not a valid path character on Windows. With this patch, %t will be expanded to C\foo. Differential Revision: http://reviews.llvm.org/D19757 llvm-svn: 268168
* [InstCombine][AVX2] Added VPERMD/VPERMPS shuffle combining placeholder tests.Simon Pilgrim2016-04-301-0/+87
| | | | | | For future support for VPERMD/VPERMPS to generic shuffles combines llvm-svn: 268166
* CodeGen: convert to range based loopsSaleem Abdulrasool2016-04-301-36/+20
| | | | | | | Convert to using some range based loops, avoid unnecessary variables for unchecked casts. NFC. llvm-svn: 268165
* [X86] Reduce memory usage of MemOp2RegOp and RegOp2MemOp folding maps.Craig Topper2016-04-302-13/+9
| | | | llvm-svn: 268164
* Add missing override.Rafael Espindola2016-04-301-1/+2
| | | | llvm-svn: 268163
* [ASan] Add shadow offset for SystemZ.Marcin Koscielnicki2016-04-301-2/+8
| | | | | | | | | | | | | | | | | | | | | | SystemZ on Linux currently has 53-bit address space. In theory, the hardware could support a full 64-bit address space, but that's not supported due to kernel limitations (it'd require 5-level page tables), and there are no plans for that. The default process layout stays within first 4TB of address space (to avoid creating 4-level page tables), so any offset >= (1 << 42) is fine. Let's use 1 << 52 here, ie. exactly half the address space. I've originally used 7 << 50 (uses top 1/8th of the address space), but ASan runtime assumes there's some space after the shadow area. While this is fixable, it's simpler to avoid the issue entirely. Also, I've originally wanted to have the shadow aligned to 1/8th the address space, so that we can use OR like X86 to assemble the offset. I no longer think it's a good idea, since using ADD enables us to load the constant just once and use it with register + register indexed addressing. Differential Revision: http://reviews.llvm.org/D19650 llvm-svn: 268161
* [InstCombine][AVX] Split off VPERMILVAR tests and added additional tests for ↵Simon Pilgrim2016-04-302-60/+124
| | | | | | UNDEF mask elements llvm-svn: 268159
* [InstCombine][AVX] VPERMILVAR to shuffle combine to use general aggregate ↵Simon Pilgrim2016-04-301-18/+20
| | | | | | | | elements. NFCI. Make use of Constant::getAggregateElement instead of checking constant types - first step towards adding support for UNDEF mask elements. llvm-svn: 268158
* Differential Revision: http://reviews.llvm.org/D19753Sriraman Tallam2016-04-301-9/+1
| | | | | | Delete Target Option PositionIndependentExecutable as PIE is now part of module flags. llvm-svn: 268155
* AMDGPU/SI: Remove wait state handling for SMRD in SIInsertWaitsTom Stellard2016-04-303-8/+4
| | | | | | This was supposed to be part of r268143. llvm-svn: 268154
* [PowerPC/QPX] Fix the load/splat peephole with overlapping readsHal Finkel2016-04-301-1/+9
| | | | | | | | | | | If, in between the splat and the load (which does an implicit splat), there is a read of the splat register, then that register must have another earlier definition. In that case, we can't replace the load's destination register with the splat's destination register. Unfortunately, I don't have a small or non-fragile test case. llvm-svn: 268152
* Reverting 268054 & 268063 as they caused PR27579.Amjad Aboud2016-04-3020-894/+86
| | | | llvm-svn: 268150
* [LowerGuardIntrinsics] Keep track of !make.implicit metadataSanjoy Das2016-04-303-1/+21
| | | | | | | | | | If a guard call being lowered by LowerGuardIntrinsics has the `!make.implicit` metadata attached, then reattach the metadata to the branch in the resulting expanded form of the intrinsic. This allows us to implement null checks as guards and still get the benefit of implicit null checks. llvm-svn: 268148
* Reroll loops with multiple IV and negative step part 3Lawrence Hu2016-04-302-9/+289
| | | | | | | | | | | | | | support multiple induction variables This patch enable loop reroll for the following case: for(int i=0; i<N; i += 2) { S += *a++; S += *a++; }; Differential Revision: http://reviews.llvm.org/D16550 llvm-svn: 268147
* [Orc] Fix the AArch64 resolver size.Lang Hames2016-04-301-1/+1
| | | | llvm-svn: 268146
* Fix a typo (NFC)Vedant Kumar2016-04-301-1/+1
| | | | llvm-svn: 268144
* AMDGPU/SI: Enable the post-ra schedulerTom Stellard2016-04-3035-117/+426
| | | | | | | | | | | | | | Summary: This includes a hazard recognizer implementation to replace some of the hazard handling we had during frame index elimination. Reviewers: arsenm Subscribers: qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18602 llvm-svn: 268143
* [LowerGuardIntrinsics] Preserve calling conv when loweringSanjoy Das2016-04-302-0/+17
| | | | llvm-svn: 268142
* add minimal test to show dropped metadataSanjay Patel2016-04-301-0/+28
| | | | llvm-svn: 268141
* remove the metadata added with r267827Sanjay Patel2016-04-301-14/+6
| | | | | | | We can demonstrate the 'select' bug and fix with a simpler test case. The merged weight values are already tested in another test. llvm-svn: 268139
* Reapply r268107 after fixing a bug breaks debug build.Xinliang David Li2016-04-292-70/+87
| | | | | | Makes the new method to set data needed by debug dump. llvm-svn: 268130
* Mark guards on true as "trivially dead"Sanjoy Das2016-04-293-11/+19
| | | | | | | | | This moves some logic added to EarlyCSE in rL268120 into `llvm::isInstructionTriviallyDead`. Adds a test case for DCE to demonstrate that passes other than EarlyCSE can now pick up on the new information. llvm-svn: 268126
* [CMake] [Xcode] Improving Xcode toolchain generation to support distribution ↵Chris Bieneman2016-04-291-0/+20
| | | | | | | | targets This adds a new target `install-distribution-toolchain` which will install an Xcode toolchain featuring just the LLVM components specified in LLVM_DISTRIBUTION_COMPONENTS. llvm-svn: 268125
* clean up documentation comments; NFCSanjay Patel2016-04-292-112/+18
| | | | llvm-svn: 268122
* [MBP] Use Function::optForSize() instead of checking OptimizeForSize directly.Haicheng Wu2016-04-293-2/+71
| | | | | | Fix a FIXME. Disable loop alignment if compiled with -Oz now. llvm-svn: 268121
* [EarlyCSE] Simplify guard intrinsicsSanjoy Das2016-04-292-0/+204
| | | | | | | | | | | | | | | | | | Summary: This change teaches EarlyCSE some basic properties of guard intrinsics: - Guard intrinsics read all memory, but don't write to any memory - After a guard has executed, the condition it was guarding on can be assumed to be true - Guard intrinsics on a constant `true` are no-ops Reviewers: reames, hfinkel Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D19578 llvm-svn: 268120
* AMDGPU: Fix crash with unreachable terminators.Matt Arsenault2016-04-292-12/+83
| | | | | | | | | | If a block has no successors because it ends in unreachable, this was accessing an invalid iterator. Also stop counting instructions that don't emit any real instructions. llvm-svn: 268119
* Revert r268107 -- debug build failureXinliang David Li2016-04-292-82/+70
| | | | llvm-svn: 268116
* [InstCombine][SSE] PSHUFB to shuffle combine to use general aggregate ↵Simon Pilgrim2016-04-291-17/+23
| | | | | | | | elements. NFCI. Make use of Constant::getAggregateElement instead of checking constant types - first step towards adding support for UNDEF mask elements. llvm-svn: 268115
* [Orc] Add ORC lazy-compilation support for AArch64.Lang Hames2016-04-292-0/+175
| | | | | | | The ORC compile callbacks and indirect stubs APIs will now work for AArc64, allowing functions to be lazily compiled and/or updated. llvm-svn: 268112
* [Orc] Make sure we don't drop the internal error in OrcRemoteTargetClient whenLang Hames2016-04-291-2/+3
| | | | | | the constructor fails, as this would lead to an 'unchecked error' crash. llvm-svn: 268111
* [Docs] Refer to the CMakePrimer from CMake docChris Bieneman2016-04-291-0/+4
| | | | | | The "Building LLVM with CMake" document should have a reference to the CMakePrimer. llvm-svn: 268109
* [ValueTracking] Make the code in lookThroughCastDavid Majnemer2016-04-291-16/+9
| | | | | | No functionality change is intended. llvm-svn: 268108
* [inliner]: Refactor inline deferring logic into its own method /NFCXinliang David Li2016-04-292-70/+82
| | | | | | | | The implemented heuristic has a large body of code which better sits in its own function for better readability. It also allows adding more heuristics easier in the future. llvm-svn: 268107
* Differential Revision: http://reviews.llvm.org/D19733Sriraman Tallam2016-04-298-22/+32
| | | | llvm-svn: 268106
* AMDGPU: Add kernarg.segment.ptr intrinsicMatt Arsenault2016-04-293-0/+30
| | | | llvm-svn: 268105
* [InstCombine] Determine the result of a select based on a dominating condition.Chad Rosier2016-04-293-1/+125
| | | | | | Differential Revision: http://reviews.llvm.org/D19550 llvm-svn: 268104
* Fix commentMatt Arsenault2016-04-291-1/+1
| | | | llvm-svn: 268102
* [InstCombine] clean up; NFCSanjay Patel2016-04-291-1/+1
| | | | llvm-svn: 268099
* [Docs] Add CMake Primer documentChris Bieneman2016-04-292-0/+466
| | | | | | | | This document is intended to provide a basic overview of the CMake scripting language for LLVM developers. It was unorthodoxly reviewed for accuracy and content on the CMake developer list: http://public.kitware.com/pipermail/cmake-developers/2016-April/028300.html llvm-svn: 268096
* AMDGPU/SI: Move post regalloc run of SIShrinkInstructionsMatt Arsenault2016-04-291-5/+1
| | | | | | | | Move to addPreEmitPass. This is so it runs after post-RA scheduling so we can merge s_nops emitted by the scheduler and hazard recognizer. llvm-svn: 268095
* DAGCombiner: Reduce truncated shl widthMatt Arsenault2016-04-2921-278/+433
| | | | llvm-svn: 268094
* [libFuzzer] fix docsKostya Serebryany2016-04-291-3/+3
| | | | llvm-svn: 268092
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