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* [globalisel][tablegen] Import stores and allow GISel to automatically ↵Daniel Sanders2017-10-238-9/+171
| | | | | | | | | | | | | | | | | substitute zero regs like WZR/XZR/$zero. This patch enables the import of stores. Unfortunately, doing so by itself, loses an optimization where storing 0 to memory makes use of WZR/XZR. To mitigate this, this patch also introduces a new feature that allows register operands to nominate a zero register. When this is done, GlobalISel will substitute (G_CONSTANT 0) with the nominated register automatically. This is currently configured to only apply to the stores. Applying it to GPR32/GPR64 register classes in general will be done after review see (https://reviews.llvm.org/D39150). llvm-svn: 316360
* Accidently merged an incomplete upstream patch in ↵Mitch Phillips2017-10-234-10/+7
| | | | | | 10e6ee563a6b5ca498f27972ca6dbe6c308f1ac2 - reverting the changes. llvm-svn: 316359
* Patch inMitch Phillips2017-10-234-7/+10
| | | | llvm-svn: 316358
* [wasm] readSection: Avoid reading past eof (fixes oss-fuzz #3219)Vedant Kumar2017-10-233-3/+7
| | | | | | | | | | | | | A wasm file crafted with a bogus section size can trigger an ASan issue in the DWARFObjInMemory constructor. Nip the problem in the bud when we read the wasm section. Found by OSS-Fuzz: https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=3219 Differential Revision: https://reviews.llvm.org/D38777 llvm-svn: 316357
* [X86][SSE] Regenerate PACKSS tests on 32 + 64-bit targetsSimon Pilgrim2017-10-231-74/+67
| | | | llvm-svn: 316354
* Updated 'Getting Started' to use valid git links (added trailing slashes)Mitch Phillips2017-10-231-33/+33
| | | | | | | | | | | | Reviewers: pcc, asl, tonic Reviewed By: pcc Subscribers: llvm-commits, kcc Differential Revision: https://reviews.llvm.org/D38516 llvm-svn: 316352
* [PassManager] add test to show the new PM uses -latesimplifycfg early; NFCSanjay Patel2017-10-231-0/+95
| | | | llvm-svn: 316351
* [globalisel] Add very brief docs summarizing the ISel part of the LLVMDev ↵Daniel Sanders2017-10-231-5/+69
| | | | | | | | tutorial. Also added links to the talks available. llvm-svn: 316350
* AMDGPU: Cleanup local atomic node namesMatt Arsenault2017-10-234-62/+51
| | | | llvm-svn: 316349
* AMDGPU: Fix default range in non-kernel functionsMatt Arsenault2017-10-233-4/+46
| | | | | | | | | The range should be assumed to be the hardware maximum if a workitem intrinsic is used in a callable function which does not know the restricted limit of the calling kernel. llvm-svn: 316346
* [X86] Fix disassembler table generation to prevent instructions tagged with ↵Craig Topper2017-10-233-16/+20
| | | | | | 'PS' being inherited into PD/XS/XD attribute entries. llvm-svn: 316345
* [MachineOutliner] NFC: Rename getters/setters to fit coding styleJessica Paquette2017-10-231-13/+13
| | | | | | | Rename endIdx, startIdx, and length to getEndIdx, getStartIdx, and getLength in Candidate. llvm-svn: 316341
* [X86] Change VMPTRST to use PS instead of TB to match VMPTRLD.Craig Topper2017-10-231-1/+1
| | | | llvm-svn: 316340
* [X86] Change RDRAND to use PS instead of TB.Craig Topper2017-10-231-3/+3
| | | | | | Should be no functional change for now. A future disassembler change will prevent disassembling with 0xf2/0xf3. llvm-svn: 316339
* [X86] Change XRSTOR to use PS instead of TB to match XSAVE.Craig Topper2017-10-231-2/+2
| | | | | | I don't think this changes anything functionally yet, but I plan to fix the disassembler to use this to disable matching certain instructions with 0xf3/0xf2/0x66 prefixes. llvm-svn: 316337
* [X86][SSE] Remove AssertZext stage from PEXTRW/PEXTRB lowering. NFCI.Simon Pilgrim2017-10-233-33/+30
| | | | | | | | Remove AssertZext and instead add PEXTRW/PEXTRB support to computeKnownBitsForTargetNode to simplify instruction selection. Differential Revision: https://reviews.llvm.org/D39169 llvm-svn: 316336
* Update DPPD/DPPS instruction scheduling on btver2.Andrew V. Tischenko2017-10-233-6/+52
| | | | | | Differential Revision: https://reviews.llvm.org/D39046 llvm-svn: 316334
* [X86] Add PTWRITE instruction for assembler and disassembler.Craig Topper2017-10-235-2/+55
| | | | llvm-svn: 316333
* [X86] Add RDPID instruction for assembler and disassembler.Craig Topper2017-10-236-3/+26
| | | | llvm-svn: 316332
* [DAGCombine] Permit combining of shuffles of equivalent splat BUILD_VECTORsSimon Pilgrim2017-10-232-9/+17
| | | | | | | | | | combineShuffleOfScalars is very conservative about shuffled BUILD_VECTORs that can be combined together. This patch adds one additional case - if both BUILD_VECTORs represent splats of the same scalar value but with different UNDEF elements, then we should create a single splat BUILD_VECTOR, sharing only the UNDEF elements defined by the shuffle mask. Differential Revision: https://reviews.llvm.org/D38696 llvm-svn: 316331
* Support formatting formatv_objects.Sam McCall2017-10-233-4/+39
| | | | | | | | | | | | | | | | Summary: Support formatting formatv_objects. While here, fix documentation about member-formatters, and attempted perfect-forwarding (I think). Reviewers: zturner Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38997 llvm-svn: 316330
* [X86][SSE] Regenerate bitcast-and-setcc testsSimon Pilgrim2017-10-233-93/+93
| | | | | | Avoid the retl/retq changes in an upcoming patch llvm-svn: 316328
* [X86][AVX2] Regenerate AVX2 intrinsics tests on 32 + 64-bit targetsSimon Pilgrim2017-10-233-2122/+1620
| | | | llvm-svn: 316326
* [X86][AVX] Regenerate AVX intrinsics tests on 32 + 64-bit targetsSimon Pilgrim2017-10-233-562/+460
| | | | llvm-svn: 316325
* [X86][F16C] Regenerate F16C schedule testsSimon Pilgrim2017-10-231-28/+28
| | | | llvm-svn: 316324
* Test commit.Artur Gainullin2017-10-231-0/+2
| | | | llvm-svn: 316322
* [llvm-dwarfdump] - Teach tool about few GNU call_sites constants.George Rimar2017-10-233-1/+124
| | | | | | | | | | | | | | This teaches tool about following consants: DW_TAG_GNU_call_site, DW_TAG_GNU_call_site_parameter, DW_AT_GNU_call_site_value, DW_AT_GNU_all_call_sites. Constants documented here: https://sourceware.org/elfutils/DwarfExtensions Differential revision: https://reviews.llvm.org/D39119 llvm-svn: 316321
* [X86] Add test for opportunity to use bzhi X86 instruction instead of ↵Ayman Musa2017-10-231-0/+97
| | | | | | | | load+and instructions. Transformation uploaded for CR in https://reviews.llvm.org/D34141. llvm-svn: 316320
* Fix for Bug 30718 - Failure to disassemble certain MOV with rex.R. The issue ↵Andrew V. Tischenko2017-10-232-2/+5
| | | | | | | | was in illegal segment register index. Differential Revision: https://reviews.llvm.org/D38786 llvm-svn: 316319
* [COFF] Improve the check for functions that should get an extra underscoreMartin Storsjo2017-10-232-5/+24
| | | | | | | | | | | This fixes exporting functions starting with an underscore, and fully decorated fastcall/vectorcall functions. Tests will be added in the lld repo. Differential Revision: https://reviews.llvm.org/D39168 llvm-svn: 316316
* Fix a -Wpedantic warning.Haojian Wu2017-10-231-1/+1
| | | | llvm-svn: 316315
* [ARM] Allow unrolling of multi-block loops.Sam Parker2017-10-232-16/+351
| | | | | | | | | | | Before, loop unrolling was only enabled for loops with a single block. This restriction has been removed and replaced by: - allow a maximum of two exiting blocks, - a four basic block limit for cores with a branch predictor. Differential Revision: https://reviews.llvm.org/D38952 llvm-svn: 316313
* [X86] Update a doxygen comment in the disassembler tablegen code. NFCCraig Topper2017-10-231-0/+1
| | | | llvm-svn: 316309
* [X86] Fix disassembly of EVEX rounding control and SAE instructions.Craig Topper2017-10-238-57/+252
| | | | | | Fixes PR31955. llvm-svn: 316308
* ExecutionEngine: make COFF Thumb2 assertions non-tautologicalSaleem Abdulrasool2017-10-221-25/+11
| | | | | | | | | The overflow detection assertions were tautological due to truncation. Adjust them to no longer be tautological. Patch by Alex Langford! llvm-svn: 316303
* Fix invalid ptrtoint in InstCombineYichao Yu2017-10-222-2/+49
| | | | | | | | | | | | | | | | | | | Summary: It's unclear if this is the only thing we can do but at least this is consistent with the check of address space agreement in `isBitCastable`. The code is used at least in both instcombine and jumpthreading though I could only find a way to trigger the invalid cast in instcombine. Reviewers: loladiro, sanjoy, majnemer Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34335 llvm-svn: 316302
* Create fewer copies of StringMaps. No functionality change intended.Benjamin Kramer2017-10-221-1/+1
| | | | llvm-svn: 316301
* [X86] Add missing override. NFC.Benjamin Kramer2017-10-221-3/+1
| | | | llvm-svn: 316299
* [SimplifyCFG] delay switch condition forwarding to -latesimplifycfgSanjay Patel2017-10-224-10/+18
| | | | | | | | | | | As discussed in D39011: https://reviews.llvm.org/D39011 ...replacing constants with a variable is inverting the transform done by other IR passes, so we definitely don't want to do this early. In fact, it's questionable whether this transform belongs in SimplifyCFG at all. I'll look at moving this to codegen as a follow-up step. llvm-svn: 316298
* [utils] Support -mtriple=powerpc64Fangrui Song2017-10-221-2/+3
| | | | | | | | | | Summary: test/CodeGen/PowerPC/pr33093.ll uses both powerpc64 (big-endian) and powerpc64le while the former was unsupported. Subscribers: nemanjai Differential Revision: https://reviews.llvm.org/D39164 llvm-svn: 316297
* Strip trailing whitespace. NFCI.Simon Pilgrim2017-10-221-2/+2
| | | | llvm-svn: 316296
* Add logic to greedy reg alloc to avoid bad eviction chainsMarina Yatsina2017-10-2210-20/+881
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes bugzilla 26810 https://bugs.llvm.org/show_bug.cgi?id=26810 This is intended to prevent sequences like: movl %ebp, 8(%esp) # 4-byte Spill movl %ecx, %ebp movl %ebx, %ecx movl %edi, %ebx movl %edx, %edi cltd idivl %esi movl %edi, %edx movl %ebx, %edi movl %ecx, %ebx movl %ebp, %ecx movl 16(%esp), %ebp # 4 - byte Reload Such sequences are created in 2 scenarios: Scenario #1: vreg0 is evicted from physreg0 by vreg1 Evictee vreg0 is intended for region splitting with split candidate physreg0 (the reg vreg0 was evicted from) Region splitting creates a local interval because of interference with the evictor vreg1 (normally region spliiting creates 2 interval, the "by reg" and "by stack" intervals. Local interval created when interference occurs.) one of the split intervals ends up evicting vreg2 from physreg1 Evictee vreg2 is intended for region splitting with split candidate physreg1 one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills Scenario #2 vreg0 is evicted from physreg0 by vreg1 vreg2 is evicted from physreg2 by vreg3 etc Evictee vreg0 is intended for region splitting with split candidate physreg1 Region splitting creates a local interval because of interference with the evictor vreg1 one of the split intervals ends up evicting back original evictor vreg1 from physreg0 (the reg vreg0 was evicted from) Another evictee vreg2 is intended for region splitting with split candidate physreg1 one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills As compile time was a concern, I've added a flag to control weather we do cost calculations for local intervals we expect to be created (it's on by default for X86 target, off for the rest). Differential Revision: https://reviews.llvm.org/D35816 Change-Id: Id9411ff7bbb845463d289ba2ae97737a1ee7cc39 llvm-svn: 316295
* [X86] More correctly support LIG and WIG for EVEX instructions in the ↵Craig Topper2017-10-221-74/+168
| | | | | | | | | | disassembler tables. This is similar to how we generate the VEX tables. More fixes are still needed for the instructions that use EVEX.b (broadcast and embedded rounding). llvm-svn: 316294
* [SimplifyCFG] try harder to forward switch condition to phi (PR34471)Sanjay Patel2017-10-222-9/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The missed canonicalization/optimization in the motivating test from PR34471 leads to very different codegen: int switcher(int x) { switch(x) { case 17: return 17; case 19: return 19; case 42: return 42; default: break; } return 0; } int comparator(int x) { if (x == 17) return 17; if (x == 19) return 19; if (x == 42) return 42; return 0; } For the first example, we use a bit-test optimization to avoid a series of compare-and-branch: https://godbolt.org/g/BivDsw Differential Revision: https://reviews.llvm.org/D39011 llvm-svn: 316293
* [ARM] Dynamic stack alignment for 16-bit ThumbMomchil Velikov2017-10-226-24/+53
| | | | | | | | | | | This patch implements dynamic stack (re-)alignment for 16-bit Thumb. When targeting processors, which support only the 16-bit Thumb instruction set the compiler ignores the alignment attributes of automatic variables and may silently generate incorrect code. Differential revision: https://reviews.llvm.org/D38143 llvm-svn: 316289
* [X86] Add a pass to convert instruction chains between domains.Guy Blank2017-10-2212-666/+3277
| | | | | | | | | | | | | | | | | The pass scans the function to find instruction chains that define registers in the same domain (closures). It then calculates the cost of converting the closure to another domain. If found profitable, the instructions are converted to instructions in the other domain and the register classes are changed accordingly. This commit adds the pass infrastructure and a simple conversion from the GPR domain to the Mask domain. Differential Revision: https://reviews.llvm.org/D37251 Change-Id: Ic2cf1d76598110401168326d411128ae2580a604 llvm-svn: 316288
* [mips] Adds support for R_MIPS_26, HIGHER, HIGHEST relocations in RuntimeDyld.Nitesh Jain2017-10-226-16/+122
| | | | | | | | | | Reviewers: sdardis Subscribers: jaydeep, bhushan, llvm-commits Differential Revision: https://reviews.llvm.org/D38314 llvm-svn: 316287
* [X86] Teach the disassembler that some instructions use VEX.W==0 without a ↵Craig Topper2017-10-224-16/+32
| | | | | | | | corresponding VEX.W==1 instruction and we shouldn't treat them as if VEX.W is ignored. Fixes PR11304. llvm-svn: 316285
* [X86] Add VEX_WIG to applicable AVX512 instructions.Craig Topper2017-10-221-41/+43
| | | | | | This should be NFC. Will be used in future patches to fix disassembler bugs. llvm-svn: 316284
* [X86] Add VEX_WIG to VROUNDSSrr/VROUNDSSrm/VROUNDSDrr/VROUNDSDrmCraig Topper2017-10-221-1/+1
| | | | llvm-svn: 316283
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