summaryrefslogtreecommitdiffstats
path: root/llvm
Commit message (Collapse)AuthorAgeFilesLines
* [CGP] fix formatting/typos in MemCmpExpansion; NFCSanjay Patel2017-06-061-36/+34
| | | | llvm-svn: 304830
* [SLP] Change extension of the test, NFC.Alexey Bataev2017-06-061-0/+0
| | | | llvm-svn: 304829
* [SLP] Add a test for fix of PR32164, NFC.Alexey Bataev2017-06-061-0/+138
| | | | llvm-svn: 304826
* llc: Add ability to parse mir from stdinMatthias Braun2017-06-063-2/+32
| | | | | | | | - Add -x <language> option to switch between IR and MIR inputs. - Change MIR parser to read from stdin when filename is '-'. - Add a simple mir roundtrip test. llvm-svn: 304825
* Fix PR23384 (part 3 of 3)Evgeny Stupachenko2017-06-0616-90/+107
| | | | | | | | | | | | | Summary: The patch makes instruction count the highest priority for LSR solution for X86 (previously registers had highest priority). Reviewers: qcolombet Differential Revision: http://reviews.llvm.org/D30562 From: Evgeny Stupachenko <evstupac@gmail.com> llvm-svn: 304824
* [DAG] remove duplicated code for isOnlyUsedInZeroEqualityComparison(); NFCISanjay Patel2017-06-061-15/+1
| | | | llvm-svn: 304822
* [LVI Printer] Rely on the LVI analysis functions rather than the LVI cacheAnna Thomas2017-06-063-91/+137
| | | | | | | | | | | | | | | | | | | | | | | Summary: LVIPrinter pass was previously relying on the LVICache. We now directly call the the LVI functions which solves the value if the LVI information is not already available in the cache. This has 2 benefits over the printing of LVI cache: 1. higher coverage (i.e. catches errors) in LVI code when cache value is invalidated. 2. relies on the core functions, and not dependent on the LVI cache (which may be scrapped at some point). It would still catch any cache invalidation errors, since we first go through the cache. Reviewers: reames, dberlin, sanjoy Reviewed by: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32135 llvm-svn: 304819
* [WebAssembly] MC: Refactor relocation handlingSam Clegg2017-06-064-161/+112
| | | | | | | | | | | | | The change cleans up and unifies the handling of relocation entries in WasmObjectWriter. Type index relocation no longer need to be handled separately. The only externally visible change should be that type index relocations are no longer grouped at the end. Differential Revision: https://reviews.llvm.org/D33918 llvm-svn: 304816
* MIRPrinter: Avoid assert() when printing empty INLINEASM strings.Matthias Braun2017-06-062-2/+21
| | | | | | | | | | | CodeGen uses MO_ExternalSymbol to represent the inline assembly strings. Empty strings for symbol names appear to be invalid. For now just special case the output code to avoid hitting an `assert()` in `printLLVMNameWithoutPrefix()`. This fixes https://llvm.org/PR33317 llvm-svn: 304815
* UnitTests: Do not use assert() for error checkingMatthias Braun2017-06-062-7/+12
| | | | | | | | | Use `if (!X) report_fatal_error()` instead of `assert()` for the ad-hoc error handling in two unittests. This reduces unnecessary differences between release and debug builds (motivated by unused variable warnings triggered in release builds). llvm-svn: 304814
* AMDGPU/NFC: Move amdgpu code object metadata to supportKonstantin Zhuravlyov2017-06-065-198/+224
| | | | | | Differential Revision: https://reviews.llvm.org/D31437 llvm-svn: 304812
* [LoopIdiom] Move X86 specific atomic memcpy test to the X86 directoryAnna Thomas2017-06-061-0/+0
| | | | | | | | | | Patch https://reviews.llvm.org/rL304806 was causing failures in Aarch64 and multiple other targets since the test should be run on X86 only. Specifying the target triple is not enough. Moving the testcase to the X86 target directory in LoopIdiom. llvm-svn: 304809
* NewGVN: Fix PR/33187. This is a bug caused by two things:Daniel Berlin2017-06-066-36/+211
| | | | | | | | | | | | | 1. When there is no perfect iteration order, we can't let phi nodes put themselves in terms of things that come later in the iteration order, or we will endlessly cycle (the normal RPO algorithm clears the hashtable to avoid this issue). 2. We are sometimes erasing the wrong expression (causing pessimism) because our equality says loads and stores are the same. We introduce an exact equality function and use it when erasing to make sure we erase only identical expressions, not equivalent ones. llvm-svn: 304807
* [Atomics][LoopIdiom] Recognize unordered atomic memcpyAnna Thomas2017-06-0610-15/+621
| | | | | | | | | | | | | | | | | | | | | | Summary: Expanding the loop idiom test for memcpy to also recognize unordered atomic memcpy. The only difference for recognizing an unordered atomic memcpy and instead of a normal memcpy is that the loads and/or stores involved are unordered atomic operations. Background: http://lists.llvm.org/pipermail/llvm-dev/2017-May/112779.html Patch by Daniel Neilson! Reviewers: reames, anna, skatkov Reviewed By: reames, anna Subscribers: llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D33243 llvm-svn: 304806
* [AMDGPU] Return correct value from SDWA passStanislav Mekhanoshin2017-06-061-1/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D33927 llvm-svn: 304805
* [WebAssembly] Remove unused methods from MCWasmObjectTargetWriterSam Clegg2017-06-063-36/+24
| | | | | | | | | | | | | These methods looks like they were originally came from MCELFObjectTargetWriter but they are never called by the WasmObjectWriter. Remove these methods meant the declaration of WasmRelocationEntry could also move into the cpp file. Differential Revision: https://reviews.llvm.org/D33905 llvm-svn: 304804
* [mips] Add madd4 subtarget featurePetar Jovanovic2017-06-066-232/+257
| | | | | | | | | | | Addition of a feature and a predicate used to control generation of madd.fmt and similar instructions. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D33400 llvm-svn: 304801
* [IRCE] Canonicalize pre/post loops after the blocks are added into parent loopAnna Thomas2017-06-062-13/+202
| | | | | | | | | | | | | | | | | | | | | Summary: We were canonizalizing the pre loop (into loop-simplify form) before the post loop blocks were added into parent loop. This is incorrect when IRCE is done on a subloop. The post-loop blocks are created, but not yet added to the parent loop. So, loop-simplification on the pre-loop incorrectly updates LoopInfo. This patch corrects the ordering so that pre and post loop blocks are added to parent loop (if any), and then the loops are canonicalized to LCSSA and LoopSimplifyForm. Reviewers: reames, sanjoy, apilipenko Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D33846 llvm-svn: 304800
* Fix spelling mistake in getRThroughput static function names. NFCI.Simon Pilgrim2017-06-061-11/+11
| | | | llvm-svn: 304799
* [X86][AVX1] Split 256-bit vector non-temporal FastISel loads to keep it ↵Simon Pilgrim2017-06-062-6/+36
| | | | | | | | non-temporal (PR32744) Extension to D33728 llvm-svn: 304798
* AMDGPU/GlobalISel: Mark 32-bit G_ICMP as legalTom Stellard2017-06-062-0/+27
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33890 llvm-svn: 304797
* Fix another ordering constraint with windows.h and comment aboutChandler Carruth2017-06-062-1/+5
| | | | | | a revers constraint that we got right (by chance). llvm-svn: 304792
* Fix several more missing headers, all of these were hidden by "lucky"Chandler Carruth2017-06-063-0/+3
| | | | | | include ordering. llvm-svn: 304790
* Add a missing #include to a header.Chandler Carruth2017-06-061-0/+1
| | | | | | | | | This was masked by lucky #include ordering in the .cpp files and uncovered when we moved to the canonical ordering because the primary header was included first (yay!). Unfortunately, I can't build this locally so took a build-bot iteration to find it. llvm-svn: 304789
* Fix one place where I missed a commented requirement for a particularChandler Carruth2017-06-061-1/+3
| | | | | | | | | include ordering. I've changed the structure so that clang-format will preserve this going forward. llvm-svn: 304788
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-06771-1082/+1057
| | | | | | | | | | | | | | | | | | | | | | | | | I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
* Re-sort #include lines for unittests. This uses a slightly modifiedChandler Carruth2017-06-0694-106/+104
| | | | | | | | | | | | | | | clang-format (https://reviews.llvm.org/D33932) to keep primary headers at the top and handle new utility headers like 'gmock' consistently with other utility headers. No other change was made. I did no manual edits, all of this is clang-format. This should allow other changes to have more clear and focused diffs, and is especially motivated by moving some headers into more focused libraries. llvm-svn: 304786
* [ARM] Add curly braces around switch case [NFC] Peter Smith2017-06-061-1/+2
| | | | | | | | | | | | | My previous commit r304702 introduced a new case into a switch statement. This case defined a variable but I forgot to add the curly brackets around the case to limit the scope. This change puts the curly braces back in so that the next person that adds a case doesn't get a build failure. Thanks to avieira for the spot. Differential Revision: https://reviews.llvm.org/D33931 llvm-svn: 304785
* [InstSimplify] Constant fold the new GEP in SimplifyGEPInst.Joey Gouly2017-06-067-8/+65
| | | | llvm-svn: 304784
* [docs] Make it clear shifts yield poison when shift amount >= bitwidthNuno Lopes2017-06-061-18/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some InstCombine optimizations already rely on the result being poison rather than undef. For example, the following rewrite is wrong if undef is used: ; (1 << Y) * X -> X << Y %Op0 = shl 1, %Y %r = mul %Op0, %Op1 => %r = shl %Op1, %Y ERROR: Mismatch in values for i4 %r Example: i4 %Y = 0x8 (8, -8) i4 %Op0 = 0x0 (0) i4 %Op1 = 0x0 (0) source: 0x0 (0) target: 0x1 (1) The optimization is correct if poison is returned instead: http://rise4fun.com/Alive/ygX Differential Revision: https://reviews.llvm.org/D33654 llvm-svn: 304780
* Vivek Pandya2017-06-0678-1462/+1540
| | | | | | | | | | | | [Improve CodeGen Testing] This patch renables MIRPrinter print fields which have value equal to its default. If -simplify-mir option is passed then MIRPrinter will not print such fields. This change also required some lit test cases in CodeGen directory to be changed. Reviewed By: MatzeB Differential Revision: https://reviews.llvm.org/D32304 llvm-svn: 304779
* Fix an unused variable warning in non-asserts builds.Chandler Carruth2017-06-061-0/+1
| | | | llvm-svn: 304778
* [InstSimplify] Remove some redundant code from InstSimplify now that ↵Craig Topper2017-06-061-13/+0
| | | | | | | | llvm::isKnownNonEqual handles vectors. isKnownNonEqual is called a little earlier in this function and can handle the case that we were checking here as well as more complex cases. llvm-svn: 304775
* [ValueTracking] Remove scalar only restriction from isKnownNonEqual. The ↵Craig Topper2017-06-061-2/+2
| | | | | | | | computeKnownBits and isKnownNonZero calls this code relies on should work fine for vectors. This will be used by another commit to remove some code from InstSimplify that is redundant for scalars, but was needed for vectors due to this issue. llvm-svn: 304774
* [InstSimplify] Use the getTrue/getFalse helpers and make sure we use the ↵Craig Topper2017-06-061-3/+1
| | | | | | | | computed result type instead of hardcoding to i1. NFC Currently, isKnownNonEqual punts on vectors so the hardcoding to i1 doesn't matter. But I plan to fix that in a future patch. llvm-svn: 304773
* [ValueTracking] Use the computeKnownBits version that returns a KnownBits ↵Craig Topper2017-06-061-6/+3
| | | | | | object instead of taking one by reference. NFC llvm-svn: 304772
* [ValueTracking] Use APInt::intersects to avoid some temporary APInts. NFCCraig Topper2017-06-061-3/+2
| | | | llvm-svn: 304771
* [InstSimplify] Use ICmpInst::isEquality predicate method. NFCCraig Topper2017-06-061-1/+1
| | | | llvm-svn: 304770
* [llvm] Remove double semicolonsMandeep Singh Grang2017-06-068-9/+9
| | | | | | | | | | | | Reviewers: craig.topper, arsenm, mehdi_amini Reviewed By: mehdi_amini Subscribers: mehdi_amini, wdng, nhaehnle, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33924 llvm-svn: 304767
* [x86] Stop this test from dirtying the source tree when run.Chandler Carruth2017-06-061-1/+1
| | | | | | The output isn't used anyways. llvm-svn: 304766
* Add a dominanance check interface that uses caching for instructions within ↵Xin Tong2017-06-065-0/+151
| | | | | | | | | | | | | | | | | | | | | | | | same basic block. Summary: This problem stems from the fact that instructions are allocated using new in LLVM, i.e. there is no relationship that can be derived by just looking at the pointer value. This interface dispatches to appropriate dominance check given 2 instructions, i.e. in case the instructions are in the same basic block, ordered basicblock (with instruction numbering and caching) are used. Otherwise, dominator tree is used. This is a preparation patch for https://reviews.llvm.org/D32720 Reviewers: dberlin, hfinkel, davide Subscribers: davide, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D33380 llvm-svn: 304764
* [x86] Add the test for folding stack spills into pextrw.Chandler Carruth2017-06-061-2/+15
| | | | | | | | This is a negative test as pextrw doesn't write to all 32-bits of the spilled GPR. This fold ended up happening when D32684 was landed and covers the regression that motivated reverting it in r304762. llvm-svn: 304763
* [x86] Revert the X86FoldTablesEmitter due to more miscompiles.Chandler Carruth2017-06-069-759/+3427
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In testing, we've found yet another miscompile caused by the new tables. And this one is even less clear how to fix (we could teach it to fold a 16-bit load instead of the 32-bit load it wants, or block folding entirely). Also, the approach to excluding instructions seems increasingly to not scale well. I have left a more detailed analysis on the review log for the original patch (https://reviews.llvm.org/D32684) along with suggested path forward. I will land an additional test case that I wrote which covers the code that was miscompiling (folding into the output of `pextrw`) in a subsequent commit to keep this a pure revert. For each commit reverted here, I've restricted the revert to the non-test code touching the x86 fold table emission until the last commit where I did revert the test updates. This means the *new* test cases added for `insertps` and `xchg` remain untouched (and continue to pass). Reverted commits: r304540: [X86] Don't fold into memory operands into insertps in the ... r304347: [TableGen] Adapt more places to getValueAsString now ... r304163: [X86] Don't fold away the memory operand of an xchg. r304123: Don't capture a temporary std::string in a StringRef. r304122: Resubmit "[X86] Adding new LLVM TableGen backend that ..." Original commit was in r304088, and after a string of fixes was reverted previously in r304121 to fix build bots, and then re-landed in r304122. llvm-svn: 304762
* [DWARF] Adding support for the DWARF v5 string offsets table ↵Wolfgang Pieb2017-06-0630-50/+1351
| | | | | | | | | | (consumer/reader part only). Reviewers: dblaikie, aprantl Differential Revision: https://reviews.llvm.org/D32779 llvm-svn: 304759
* CodeGen: Refactor MIR parsingMatthias Braun2017-06-0619-167/+147
| | | | | | | | | | | | When parsing .mir files immediately construct the MachineFunctions and put them into MachineModuleInfo. This allows us to get rid of the delayed construction (and delayed error reporting) through the MachineFunctionInitialzier interface. Differential Revision: https://reviews.llvm.org/D33809 llvm-svn: 304758
* [cmake] Enable reverse iteration by default through build macroMandeep Singh Grang2017-06-063-0/+11
| | | | | | | | | | | | | | | | | | Summary: Reverse iteration can be turned on, by default, by setting -DLLVM_REVERSE_ITERATION:BOOL=ON during cmake. With this enabled, we can uncover lots of cases of non-determinism in codegen by simply running our tests (without any other change). We can then setup a buildbot which will have this turned on by default. Initially, a lot of unit tests will fail in this configuration. Once we start fixing non-determinism issues, we can gradually make this a blocker for patches. Reviewers: davide, dblaikie, mehdi_amini, dberlin Reviewed By: dblaikie Subscribers: probinson, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D33908 llvm-svn: 304757
* llc: Create custom pass pipeline for .mir files; NFCIMatthias Braun2017-06-061-34/+46
| | | | | | | | | | Create a custom pass pipeline when loading .mir files even in --start-after/--start-before cases. This streamlines the mir handling code and prepares for an upcoming commit. llvm-svn: 304755
* CodeGen/LLVMTargetMachine: Refactor ISel pass construction; NFCIMatthias Braun2017-06-066-102/+123
| | | | | | | | | | | | - Move ISel (and pre-isel) pass construction into TargetPassConfig - Extract AsmPrinter construction into a helper function Putting the ISel code into TargetPassConfig seems a lot more natural and both changes together make make it easier to build custom pipelines involving .mir in an upcoming commit. This moves MachineModuleInfo to an earlier place in the pass pipeline which shouldn't have any effect. llvm-svn: 304754
* [x86] fix over-specific triple; NFCSanjay Patel2017-06-061-18/+18
| | | | | | | | There's nothing darwin-specific in these tests, and using that setting causes extra phantom diffs when the auto-generated check lines are regenerated today. llvm-svn: 304753
* [InlineSpiller] Don't spill fully undef valuesQuentin Colombet2017-06-052-2/+91
| | | | | | | | | | Althought it is not wrong to spill undef values, it is useless and harms both code size and runtime. Before spilling a value, check that its content actually matters. http://www.llvm.org/PR33311 llvm-svn: 304752
OpenPOWER on IntegriCloud