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* Implement initial-exec TLS model for 32-bit PIC x86Hans Wennborg2012-05-115-20/+48
| | | | | | | This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong code here (see the update to test/CodeGen/X86/tls-pie.ll). llvm-svn: 156611
* Added the missing bit definition for the 4th bit of the STR (post reg) ↵Silviu Baranga2012-05-114-0/+72
| | | | | | instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. llvm-svn: 156609
* Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate ↵Silviu Baranga2012-05-113-3/+12
| | | | | | offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate. llvm-svn: 156608
* Fix a use after free when the streamer is destroyed. Fixes pr12622.Rafael Espindola2012-05-111-1/+1
| | | | llvm-svn: 156606
* Fix a misleading comment.Akira Hatanaka2012-05-111-1/+1
| | | | llvm-svn: 156603
* Tidy up. Trailing whitespace.Jim Grosbach2012-05-1112-35/+35
| | | | llvm-svn: 156602
* Tidy up. Trailing whitespace.Jim Grosbach2012-05-118-55/+55
| | | | llvm-svn: 156601
* Fix a minor logic mistake transforming compares in instcombine. PR12514.Eli Friedman2012-05-112-1/+16
| | | | llvm-svn: 156600
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-113-27/+162
| | | | | | | | | | | | | | | | | This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 llvm-svn: 156599
* Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),Dan Gohman2012-05-118-2/+55
| | | | | | but it generates int3 on x86 instead of ud2. llvm-svn: 156593
* Allow unique_file to take a mode for file permissions, but defaultEric Christopher2012-05-113-7/+10
| | | | | | | | to user only read/write. Part of rdar://11325849 llvm-svn: 156591
* Fix intendation.Chad Rosier2012-05-101-1/+1
| | | | llvm-svn: 156589
* Compute secondary sub-registers.Jakob Stoklund Olesen2012-05-102-3/+161
| | | | | | | | | | | | | | | | | | | | | | The sub-registers explicitly listed in SubRegs in the .td files form a tree. In a complicated register bank, it is possible to have sub-register relationships across sub-trees. For example, the ARM NEON double vector Q0_Q1 is a tree: Q0_Q1 = [Q0, Q1], Q0 = [D0, D1], Q1 = [D2, D3] But we also define the DPair register D1_D2 = [D1, D2] which is fully contained in Q0_Q1. This patch teaches TableGen to find such sub-register relationships, and assign sub-register indices to them. In the example, TableGen will create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a sub-register of Q0_Q1. This will eventually enable the coalescer to handle copies of skewed sub-registers. llvm-svn: 156587
* objectsize: add support for GEPs with non-constant indexesNuno Lopes2012-05-104-34/+59
| | | | | | add an additional parameter to InstCombiner::EmitGEPOffset() to force it to *not* emit operations with NUW flag llvm-svn: 156585
* Added X86 Atom latencies for instructions in X86InstrInfo.td.Preston Gurd2012-05-103-223/+426
| | | | llvm-svn: 156579
* Add support for the 'X' inline asm operand modifier.Eric Christopher2012-05-102-4/+31
| | | | | | Patch by Jack Carter. llvm-svn: 156577
* misched: Print machineinstrs with -debug-only=mischedAndrew Trick2012-05-101-0/+2
| | | | llvm-svn: 156576
* misched: tracing register pressure heuristics.Andrew Trick2012-05-101-6/+22
| | | | llvm-svn: 156575
* misched: Add register pressure backoff to ConvergingScheduler.Andrew Trick2012-05-101-38/+144
| | | | | | | | | | | Prioritize the instruction that comes closest to keeping pressure under the target's limit. Then prioritize instructions that avoid increasing the max pressure in the scheduled region. The max pressure heuristic is a tad aggressive. Later I'll fix it to consider the unscheduled pressure as well. WIP: This is mostly functional but untested and not likely to do much good yet. llvm-svn: 156574
* misched: Release only unscheduled nodes into ReadyQ.Andrew Trick2012-05-101-2/+8
| | | | llvm-svn: 156573
* misched: Added ReadyQ container wrapper for Top and Bottom Queues.Andrew Trick2012-05-101-11/+44
| | | | llvm-svn: 156572
* misched: Introducing Top and Bottom register pressure trackers during ↵Andrew Trick2012-05-103-39/+112
| | | | | | scheduling. llvm-svn: 156571
* Hexagon V5 Support - V5 td file.Sirish Pande2012-05-101-0/+626
| | | | llvm-svn: 156569
* Hexagon V5 FP Support.Sirish Pande2012-05-1029-194/+862
| | | | llvm-svn: 156568
* RegPressure: API for speculatively checking instruction pressure.Andrew Trick2012-05-102-1/+229
| | | | | | | | | Added getMaxExcessUpward/DownwardPressure. They somewhat abuse the tracker by speculatively handling an instruction out of order. But it is convenient for now. In the future, we will cache each instruction's pressure contribution to make this efficient. llvm-svn: 156561
* RegPressure: fix array index iteration style.Andrew Trick2012-05-101-8/+8
| | | | llvm-svn: 156560
* Teach DeadStoreElimination to eliminate exit-block stores with phi addresses.Dan Gohman2012-05-104-3/+68
| | | | llvm-svn: 156558
* Revert: 156550 "ARM: peephole optimization to remove cmp instruction"Manman Ren2012-05-103-161/+27
| | | | | | This commit broke an external linux bot and gave a compile-time warning. llvm-svn: 156556
* Precompute lists of explicit sub-registers and indices.Jakob Stoklund Olesen2012-05-102-19/+38
| | | | | | | | The .td files specify a tree of sub-registers. Store that tree as ExplicitSubRegs lists in CodeGenRegister instead of extracting it from the Record when needed. llvm-svn: 156555
* Rewrite ScalarEvolution::hasOperand to use an explicit worklist insteadDan Gohman2012-05-101-35/+50
| | | | | | of recursion, to avoid excessive stack usage on deep expressions. llvm-svn: 156554
* teach DSE and isInstructionTriviallyDead() about callocNuno Lopes2012-05-103-5/+26
| | | | llvm-svn: 156553
* formatting change: strip debug info from testJoel Jones2012-05-101-293/+83
| | | | llvm-svn: 156551
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-103-27/+161
| | | | | | | | | | | | | | | | | This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 llvm-svn: 156550
* Fix a problem with incomplete equality testing of PHINodes in Joel Jones2012-05-102-1/+427
| | | | | | | | | | | | | | | | | | | | Instruction::IsIdenticalToWhenDefined. This manifested itself when inlining two calls to the same function. The inlined function had a switch statement that returned one of a set of global variables. Without this modification, the two phi instructions that chose values from the branches of the switch instruction inlined from the callee were considered equivalent and jump-threading replaced a load for the first switch value with a phi selecting from the second switch, thereby producing incorrect code. This patch has been tested with "make check-all", "lnt runteste nt", and llvm self-hosted, and on the original program that had this problem, wireshark. <rdar://problem/11025519> llvm-svn: 156548
* Fix merge-typo and cleanupNadav Rotem2012-05-101-5/+3
| | | | llvm-svn: 156541
* AVX2: Add an additional broadcast idiom.Nadav Rotem2012-05-102-2/+17
| | | | llvm-svn: 156540
* Generate AVX/AVX2 shuffles even when there is a memory op somewhere else in ↵Nadav Rotem2012-05-102-4/+17
| | | | | | | | | | the program. Starting r155461 we are able to select patterns for vbroadcast even when the load op is used by other users. Fix PR11900. llvm-svn: 156539
* Fix TableGen's RegPressureSet weight normalization to handle subreg DAGS.Andrew Trick2012-05-101-4/+9
| | | | | | I initially assumed that the subreg graph was a tree. That may not be true. llvm-svn: 156524
* ExecutionEngine: Check for NULL ErrorStr before using it.Jim Grosbach2012-05-101-2/+3
| | | | | | Patch by Yury Mikhaylov <yury.mikhaylov@gmail.com>. llvm-svn: 156523
* Fix warning text.Jakob Stoklund Olesen2012-05-091-1/+1
| | | | llvm-svn: 156521
* Fix the objc_storeStrong recognizer to stop before walking off theDan Gohman2012-05-092-1/+38
| | | | | | end of a basic block if there's no store. llvm-svn: 156520
* Compute a backwards SubReg -> SubRegIndex map for each register.Jakob Stoklund Olesen2012-05-092-0/+23
| | | | | | | | | | | | | | | | This mapping is for internal use by TableGen. It will not be exposed in the generated files. Unfortunately, the mapping is not completely well-defined. The X86 xmm registers appear with multiple sub-register indices in the ymm registers. This is because of the odd idempotent sub_sd and sub_ss sub-register indices. I hope to be able to eliminate them entirely, so we can require the sub-registers to form a tree. For now, just place the canonical sub_xmm index in the mapping, and ignore the idempotents. llvm-svn: 156519
* Rename getSubRegs() to computeSubRegs().Jakob Stoklund Olesen2012-05-092-10/+11
| | | | | | That's what it does. llvm-svn: 156518
* objectsize:Nuno Lopes2012-05-092-66/+97
| | | | | | | refactor code a bit to enable future changes to support run-time information add support to compute allocation sizes at run-time if penalty > 1 (e.g., malloc(x), calloc(x, y), and VLAs) llvm-svn: 156515
* Add unittests for Triple::getMacOSXVersion and Triple::getiOSVersion.Chad Rosier2012-05-091-0/+65
| | | | llvm-svn: 156507
* Added a regress test for the bug #9964 before close it.Danil Malyshev2012-05-091-0/+9
| | | | | | This bug was fixed by Jim Grosbach in #138879, thanks Jim! llvm-svn: 156505
* Mark .opd @progbits, thus avoiding a warning from asm.Roman Divacky2012-05-091-1/+1
| | | | llvm-svn: 156494
* Set the default iOS version to 3.0.Chad Rosier2012-05-091-2/+4
| | | | llvm-svn: 156492
* Use the cpuid 64 bit flag to pick the default CPU name for an unknown model.Bob Wilson2012-05-091-1/+1
| | | | | | | | | | | For the Family 6 switch in sys::getHostCPUName, an unrecognized model was reported as "i686". That's a really bad default since it means that new CPUs will be treated as if they can only use 32-bit code. This just looks at the cpuid extended feature flag for 64 bit support, and if that is set, it uses a default x86-64 cpu. Similar logic is already used for the Family 15 code. <rdar://problem/11314502> llvm-svn: 156486
* Don't return true on a function with a void return type.Chad Rosier2012-05-091-1/+1
| | | | llvm-svn: 156484
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