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* Redirect DataLayout from TargetMachine to Module in GlobalMergeMehdi Amini2015-07-071-13/+16
| | | | | | | | | | | | | | | | Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10987 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 241615
* Redirect DataLayout from TargetMachine to Module in CodeGen PrepareMehdi Amini2015-07-071-27/+28
| | | | | | | | | | | | | | | | Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10986 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 241614
* Redirect DataLayout from TargetMachine to Module in FastISelMehdi Amini2015-07-071-1/+1
| | | | | | | | | | | | | | | | Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10985 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 241613
* Add a pattern for a nvcast from v2f64 -> v4f32Arnold Schwaighofer2015-07-072-0/+9
| | | | | | | | | Since the NvCast is generated by the selection process the concerns about endianess and bit reversal don't apply. rdar://21703486 llvm-svn: 241611
* Redirect DataLayout from TargetMachine to Module in MachineFunctionMehdi Amini2015-07-073-24/+28
| | | | | | | | | | | | | | | | Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10984 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 241610
* Use default member initializers to deduplicate code in ↵Reid Kleckner2015-07-071-50/+19
| | | | | | X86MachineFunctionInfo, NFC llvm-svn: 241609
* Fix the -DBUILD_SHARED_LIBS=ON build.Rafael Espindola2015-07-074-2/+9
| | | | llvm-svn: 241608
* MIR Parser: wrap 'MBBSlots' from the MI parsing functions in a struct. NFC.Alex Lorenz2015-07-073-33/+32
| | | | | | | | | | | This commit modifies the interface for the machine instruction parsing functions by wrapping the parameter 'MBBSlots' in a new structure called 'PerFunctionMIParsingState'. This change is useful as in the future I will be able to pass new parameters to the machine instruction parser just by modifying the 'PerFunctionMIParsingState' structure instead of adding a new parameter to each function. llvm-svn: 241607
* Delete UnknownAddress. It is a perfectly valid symbol value.Rafael Espindola2015-07-0715-71/+41
| | | | | | | | | | | getSymbolValue now returns a value that in convenient for most callers: * 0 for undefined * symbol size for common symbols * offset/address for symbols the rest Code that needs something more specific can check getSymbolFlags. llvm-svn: 241605
* Simplify by passing in the section of the symbol. NFC.Rafael Espindola2015-07-071-22/+5
| | | | llvm-svn: 241603
* Revert r241570, it caused PR24053Nico Weber2015-07-071-22/+29
| | | | llvm-svn: 241602
* [Hexagon] Fix unused variable warnings in NDEBUG build caused by r241595Krzysztof Parzyszek2015-07-072-12/+8
| | | | llvm-svn: 241600
* Fix bug in test-release.sh where the script would not exit if anyDan Liew2015-07-071-1/+5
| | | | | | | | | | | | | | of the build stages that are sent through a pipe (e.g. tee) failed. This potentially allowed builds and/or tests to fail without anyone noticing. It appears that for the LLVM 3.6.[01] releases this actually happened for the Ubuntu 14.04LTS binary releases. The essence of the issue is that without ``set -o pipefail`` the following command in bash has a zero exit code. false | tee /dev/null ; exit $? llvm-svn: 241599
* [WinEH] Add a report_fatal_error for 32-bit stack realignmentReid Kleckner2015-07-071-0/+5
| | | | | | | | | This type of prologue isn't supported yet. Implementing it should be a matter of copying the adjusted incoming EBP into ESI (the base pointer) instead of EBP. The original EBP can be saved and restored from other memory afterwards. llvm-svn: 241597
* [Hexagon] Implement bit-tracking facility with specifics for HexagonKrzysztof Parzyszek2015-07-075-0/+2832
| | | | | | | | This includes code that is intended to be target-independent as well as the Hexagon-specific details. This is just the framework without any users. llvm-svn: 241595
* Common symbols don't have a value.Rafael Espindola2015-07-073-8/+15
| | | | | | | | | | | | | At least not in the interface exposed by ObjectFile. This matches what ELF and COFF implement. Adjust existing code that was expecting them to have values. No overall functionality change intended. Another option would be to change the interface and the ELF and COFF implementations to say that the value of a common symbol is its size. llvm-svn: 241593
* use range-based for loops; NFCISanjay Patel2015-07-071-35/+17
| | | | llvm-svn: 241592
* Fix test case to unbreak build.Akira Hatanaka2015-07-071-9/+18
| | | | | | | | This commit changes the target arch to fix the test case commited in r241566 that was failing on ninja-x64-msvc-RA-centos6. Also add checks to make sure the callee's address is loaded to blx's operand. llvm-svn: 241588
* Common symbols are not undefined, at least for ObjectFile.Rafael Espindola2015-07-072-3/+11
| | | | | | | | | They are implemented like that in some object formats, but for the interface provided by lib/Object, SF_Undefined and SF_Common are different things. This matches the ELF and COFF implementation and fixes llvm-nm for MachO. llvm-svn: 241587
* Simplify, NFC.Rafael Espindola2015-07-071-3/+2
| | | | | | | | In these two contexts we really just want the raw n_value. No need to use getSymbolValue which checks for special cases where, semantically, the symbol has no value. llvm-svn: 241584
* [IR] Make getFirstNonPHI return null if the BB is emptyDavid Majnemer2015-07-071-29/+22
| | | | | | | | | | | | getFirstNonPHI's documentation states that it returns null if there is no non-PHI instruction. However, it instead returns a pointer to the end iterator. The implementation of getFirstNonPHI claims that dereferencing the iterator will result in an assertion failure but this doesn't occur. Instead, machinery like getFirstInsertionPt will attempt to isa<> this invalid memory which results in unpredictable behavior. Instead, make getFirst* return null if no such instruction exists. llvm-svn: 241570
* Fix gcc warnings of different enum and non-enum types in ternariesDenis Protivensky2015-07-072-9/+9
| | | | llvm-svn: 241567
* [ARM] Define a subtarget feature and use it to decide whether long calls shouldAkira Hatanaka2015-07-0710-21/+63
| | | | | | | | | | | | | | | | | be emitted. This is needed to enable ARM long calls for LTO and enable and disable it on a per-function basis. Out-of-tree projects currently using EnableARMLongCalls to emit long calls should start passing "+long-calls" to the feature string (see the changes made to clang in r241565). rdar://problem/21529937 Differential Revision: http://reviews.llvm.org/D9364 llvm-svn: 241566
* Fix \param in r241472. [-Wdocumentation]NAKAMURA Takumi2015-07-071-1/+1
| | | | llvm-svn: 241552
* MIR Parser: Verify the implicit machine register operands.Alex Lorenz2015-07-0713-31/+230
| | | | | | | | | | | | This commit verifies that the parsed machine instructions contain the implicit register operands as specified by the MCInstrDesc. Variadic and call instructions aren't verified. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10781 llvm-svn: 241537
* [StackMap Liveness] Calling the base class' getAnalysisUsage method. NFCI.Juergen Ributzka2015-07-071-2/+1
| | | | | | | | Calling into the base class' getAnalysisUsage method after we did our pass specific modifications. This shouldn't really matter since this is the last pass in the pipeline anyways. llvm-svn: 241536
* [StackMap Liveness] No need to cache the MachineFunction. NFC.Juergen Ributzka2015-07-071-22/+20
| | | | | | Don't cache the MachineFunction in the pass and range'ify some loops. llvm-svn: 241535
* [Triple] Add a helper to switch between big/little endian variantsBenjamin Kramer2015-07-063-0/+210
| | | | | | This will be used from clang's driver. llvm-svn: 241527
* Make UnitTestMain/TestMain.cpp free from llvm/Config/config.h.NAKAMURA Takumi2015-07-061-3/+2
| | | | | | llvm/Config/config.h is unavailable outside of build tree. llvm-svn: 241523
* [FaultMaps] Add statistic to count the # of implicit null checks.Sanjoy Das2015-07-061-0/+8
| | | | llvm-svn: 241521
* [WebAssembly] Create a CodeGen unittest directory.Dan Gohman2015-07-061-0/+2
| | | | llvm-svn: 241520
* MIR Serialization: Serialize the implicit register flag.Alex Lorenz2015-07-067-23/+119
| | | | | | | | | | | | | | This commit serializes the implicit flag for the register machine operands. It introduces two new keywords into the machine instruction syntax: 'implicit' and 'implicit-def'. The 'implicit' keyword is used for the implicit register operands, and the 'implicit-def' keyword is used for the register operands that have both the implicit and the define flags set. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10709 llvm-svn: 241519
* Remove JumpInstrTableInfo.h as it is no longer used.Eric Christopher2015-07-062-72/+0
| | | | llvm-svn: 241517
* [X86][AVX] Add support for shuffle decoding of vperm2f128/vperm2i128 with ↵Simon Pilgrim2015-07-063-15/+18
| | | | | | | | | | | | zero'd lanes The vperm2f128/vperm2i128 shuffle mask decoding was not attempting to deal with shuffles that give zero lanes. This patch fixes this so that the assembly printer can provide shuffle comments. As this decoder is also used in X86ISelLowering for shuffle combining, I've added an early-out to match existing behaviour. The hope is that we can add zero support in the future, this would allow other ops' decodes (e.g. insertps) to be combined as well. Differential Revision: http://reviews.llvm.org/D10593 llvm-svn: 241516
* [x86] extend machine combiner reassociation optimization to SSE scalar addsSanjay Patel2015-07-062-55/+108
| | | | | | | | | | | | Extend the reassociation optimization of http://reviews.llvm.org/rL240361 (D10460) to SSE scalar FP SP adds in addition to AVX scalar FP SP adds. With the 'switch' in place, we can trivially add other opcodes and test cases in future patches. Differential Revision: http://reviews.llvm.org/D10975 llvm-svn: 241515
* [X86][SSE] Vectorized i64 uniform constant SRA shiftsSimon Pilgrim2015-07-067-81/+106
| | | | | | | | This patch adds vectorization support for uniform constant i64 arithmetic shift right operators. Differential Revision: http://reviews.llvm.org/D9645 llvm-svn: 241514
* WebAssembly: add some TODOJF Bastien2015-07-061-0/+11
| | | | | | | | | | Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D10971 llvm-svn: 241513
* llvm-nm: treat weak undefined as undefined.Rafael Espindola2015-07-063-14/+29
| | | | | | This matches the behavior of gnu ld. llvm-svn: 241512
* [WinEH] Add some test cases I forgot to add to previous commitsReid Kleckner2015-07-062-0/+258
| | | | llvm-svn: 241510
* [WinEH] Insert the EH code load before the block terminatorReid Kleckner2015-07-062-1/+67
| | | | | | | The previous code put the load after the terminator, leading to invalid IR and downstream crashes. This caused http://crbug.com/506446. llvm-svn: 241509
* [X86][SSE4A] Shuffle lowering using SSE4A EXTRQ/INSERTQ instructionsSimon Pilgrim2015-07-069-6/+521
| | | | | | | | | | | | This patch adds support for v8i16 and v16i8 shuffle lowering using the immediate versions of the SSE4A EXTRQ and INSERTQ instructions. Although rather limited (they can only act on the lower 64-bits of the source vectors, leave the upper 64-bits of the result vector undefined and don't have VEX encoded variants), the instructions are still useful for the zero extension of any lane (EXTRQ) or inserting a lane into another vector (INSERTQ). Testing demonstrated that it wasn't typically worth it to use these instructions for v2i64 or v4i32 vector shuffles although they are capable of it. As well as adding specific pattern matching for the shuffles, the patch uses EXTRQ for zero extension cases where SSE41 isn't available and its more efficient than the SSE2 'unpack' default approach. It also adds shuffle decode support for the EXTRQ / INSERTQ cases when the instructions are handling full byte-sized extractions / insertions. From this foundation, future patches will be able to make use of the instructions for situations that use their ability to extract/insert at the bit level. Differential Revision: http://reviews.llvm.org/D10146 llvm-svn: 241508
* [X86][SSE] Use the general SMAX/SMIN/UMAX/UMIN opcodes and remove the X86 ↵Simon Pilgrim2015-07-066-138/+177
| | | | | | | | | | | | implementation With the completion of D9746 there is now a common implementation of integer signed/unsigned min/max nodes, removing the need for the equivalent X86 specific implementations. This patch removes the old X86ISD nodes, legalizes the relevant SSE2/SSE41/AVX2/AVX512 instructions for the ISD versions and converts the small amount of existing X86 code. Differential Revision: http://reviews.llvm.org/D10947 llvm-svn: 241506
* [TwoAddressInstructionPass] Rename a variable to match the coding style.Quentin Colombet2015-07-061-4/+4
| | | | | | Spot by Bruno. llvm-svn: 241505
* Swap operands instead of using !.Rafael Espindola2015-07-061-1/+1
| | | | | | | | This avoids returning true for A == B. Thanks to Benjamin Kramer for noticing it. llvm-svn: 241490
* When sorting by address, undefined symbols go first.Rafael Espindola2015-07-062-16/+21
| | | | | | This matches gnu nm. llvm-svn: 241488
* Reduce code duplication. NFC.Rafael Espindola2015-07-061-41/+17
| | | | llvm-svn: 241484
* [llvm-extract] Drop comdats from declarationsReid Kleckner2015-07-062-4/+13
| | | | | | The verifier rejects comdats on declarations. llvm-svn: 241483
* Fix printing of common symbols.Rafael Espindola2015-07-062-4/+12
| | | | | | Printing the symbol size matches the behavior or both gnu nm and freebsd nm. llvm-svn: 241480
* llc: Add a 'run-pass' option.Alex Lorenz2015-07-069-42/+81
| | | | | | | | | | | | | | | This commit adds a 'run-pass' option to llc, which instructs the compiler to run one specific code generation pass only. Llc already has the 'start-after' and the 'stop-after' options, and this new option complements the other two by making it easier to write tests that want to invoke a single pass only. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10776 llvm-svn: 241476
* AMDGPU: Run SIInsertWaits as pre-emit passMatt Arsenault2015-07-061-1/+1
| | | | | | | | | | | Running this after the scheduler enables scheduling waits later so other ALU instructions can run while this would be waiting. When combined with enabling the post-RA scheduler, this gives about a ~20% improvement on sgemm. llvm-svn: 241473
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