| Commit message (Collapse) | Author | Age | Files | Lines |
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caching it. The TLI may change between functions. No functionality change.
llvm-svn: 184349
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llvm-svn: 184348
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already.
llvm-svn: 184346
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I have had several requests to expose these two methods as public for various
potential optimizations.
llvm-svn: 184345
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llvm-svn: 184344
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Register it with PassManager
llvm-svn: 184343
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Prior to this change, the considered addressing modes may be invalid since the
maximum and minimum offsets were not taking into account.
This was causing an assertion failure.
The added test case exercices that behavior.
<rdar://problem/14199725> Assertion failed: (CurScaleCost >= 0 && "Legal
addressing mode has an illegal cost!")
llvm-svn: 184341
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llvm-svn: 184338
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This matches GNU ar behavior. Also remove the now unused getFileStatus method.
Not sure how to add a test, it would have to run ls -l or something like that.
llvm-svn: 184337
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llvm-svn: 184328
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ExtractElementInst).
llvm-svn: 184325
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llvm-svn: 184320
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llvm-svn: 184318
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The type <3 x i8> is a common in graphics and we want to be able to vectorize it.
This changes accelerates bullet by 12% and 471_omnetpp by 5%.
llvm-svn: 184317
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llvm-svn: 184316
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llvm-svn: 184315
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llvm-svn: 184311
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It is not present in GNU or OS X versions and doesn't make a lot of sense
for llvm-ar.
llvm-svn: 184306
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llvm-svn: 184305
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llvm-svn: 184298
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on the target specific operand to call to add the target specific operand to an MCInst. This patch defines RenderMethod for mips RegisterOperand classes and removes redundant code from MipsAsmParser.cpp
llvm-svn: 184292
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std::string instead.
llvm-svn: 184291
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llvm-svn: 184286
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llvm-svn: 184282
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llvm-svn: 184281
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llvm-svn: 184278
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There were only two places it was actually making anything shorter.
llvm-svn: 184273
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llvm-svn: 184272
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Not sure why we weren't catching this with -Wunused-parameter...
Spotted by inspection.
llvm-svn: 184271
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llvm-svn: 184269
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llvm-svn: 184268
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llvm-svn: 184267
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llvm-svn: 184263
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llvm-svn: 184261
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Previously, we would monkeypatch the vector of YAML::Section's in order
to ensure that the SHT_NULL entry is present. Now we just add it
unconditionally.
The proliferation of small numerical adjustments is beginning to
frighten me, but I can't think of a way having a single point of truth
for them without introducing a whole new layer of data structures (i.e.
lots of code and complexity) between the YAML and binary ELF formats.
llvm-svn: 184260
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llvm-svn: 184258
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Currently, we only output the name.
llvm-svn: 184255
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The information was correct pre-LPAE.
llvm-svn: 184253
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llvm-svn: 184247
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rdar://14194152
llvm-svn: 184244
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This will be needed later for holding symbol names, due to the libObject
issue mentioned in the commit message of r184161.
llvm-svn: 184242
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llvm-svn: 184239
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llvm-svn: 184236
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llvm-svn: 184235
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llvm-svn: 184233
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implying that upper bits are always 0.
llvm-svn: 184231
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AddCombineTo64bitMLAL.
Said assert assumes that ADDC will always have a glue node as its second
argument and is checked before we even know that we are actually performing the
relevant MLAL optimization. This is incorrect since on ARM we *CAN* codegen ADDC
with a use list based second argument. Thus to have both effects, I converted
the assert to a conditional check which if it fails we do not perform the
optimization.
In terms of tests I can not produce an ADDC from the IR level until I get in my
multiprecision optimization patch which is forthcoming. The tests for said patch
would cause this assert to fail implying that said tests will provide the
relevant tests.
llvm-svn: 184230
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llvm-svn: 184229
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llvm-svn: 184228
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"When assembling to the ARM instruction set, the .N qualifier produces
an assembler error and the .W qualifier has no effect."
In the pre-matcher handler in the asm parser the ".w" (wide) qualifier
when in ARM mode is now discarded. And an error message is now
produced when the ".n" (narrow) qualifier is used in ARM mode.
Test cases for these were added.
rdar://14064574
llvm-svn: 184224
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