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* Revert r291092 because it introduces a crash.Michael Kuperstein2017-01-092-170/+0
| | | | | | See PR31589 for details. llvm-svn: 291478
* X86-specific path: Implemented the fusing of MUL+ADDSUB to FMADDSUB.Vyacheslav Klochkov2017-01-092-41/+283
| | | | | | Differential Revision: https://reviews.llvm.org/D28087 llvm-svn: 291473
* [InstCombine] add test to show missed fold using llvm.assume; NFCSanjay Patel2017-01-091-0/+13
| | | | llvm-svn: 291472
* Revert "[ObjectYAML] Support for DWARF line tables"Chris Bieneman2017-01-099-1004/+12
| | | | | | | | This reverts commit r291470 due to failing bots: http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/47209/steps/test_llvm/logs/stdio llvm-svn: 291471
* [ObjectYAML] Support for DWARF line tablesChris Bieneman2017-01-099-12/+1004
| | | | | | This patch adds support for the DWARF debug_lines section. The line table state machine opcodes are preserved, so this can be used to test the state machine evaluation directly. llvm-svn: 291470
* [InstCombine] regenerate checks; NFCSanjay Patel2017-01-091-13/+12
| | | | llvm-svn: 291469
* [ValueTracking] regenerate checks; NFCSanjay Patel2017-01-091-7/+15
| | | | llvm-svn: 291468
* Fix function regex in update_tests so it can handle {}'s in function argsDaniel Berlin2017-01-091-1/+1
| | | | llvm-svn: 291467
* [InstCombine] regenerate checks; NFCSanjay Patel2017-01-091-66/+63
| | | | llvm-svn: 291464
* [InstCombine] remove unnecessary attribute comments from test files; NFCSanjay Patel2017-01-092-21/+0
| | | | llvm-svn: 291463
* [LV] Fix-up external IV users after updating dominator treeMatthew Simpson2017-01-092-7/+65
| | | | | | | | | | | | | This patch delays the fix-up step for external induction variable users until after the dominator tree has been properly updated. This should fix PR30742. The SCEVExpander in InductionDescriptor::transform can generate code in the wrong location if the dominator tree is not up-to-date. We should work towards keeping the dominator tree up-to-date throughout the transformation. Reference: https://llvm.org/bugs/show_bug.cgi?id=30742 Differential Revision: https://reviews.llvm.org/D28168 llvm-svn: 291462
* AMDGPU: Add Assert[SZ]Ext during argument load creationMatt Arsenault2017-01-093-88/+114
| | | | | | | | | | | For i16 zeroext arguments when i16 was a legal type, the known bits information from the truncate was lost. Insert a zeroext so the known bits optimizations work with the 32-bit loads. Fixes code quality regressions vs. SI in min.ll test. llvm-svn: 291461
* Reapply r291025 ("AMDGPU: Remove unneccessary intermediate vector")Matt Arsenault2017-01-091-19/+33
| | | | llvm-svn: 291460
* Intrinsic::Bitreverse is safe to speculateXin Tong2017-01-092-0/+28
| | | | | | | | | | | | Summary: Intrinsic::Bitreverse is safe to speculate Reviewers: hfinkel, mkuper, arsenm, jmolloy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28471 llvm-svn: 291456
* In the below scenario, we must be able to skip the a DBG_VALUE instruction andSumanth Gundapaneni2017-01-091-3/+8
| | | | | | | | | | | | | | | remove the dead store. %vreg0<def> = L2_loadri_io <fi#15>, 0; mem:LD4[%dataF](align=4) DBG_VALUE %vreg0, %noreg, !"dataF", <!184>; IntRegs:%vreg0 S2_storeri_io <fi#15>, 0, %vreg0; mem:ST4[%dataF] In reality, this kind of stores are eliminated before Stack Slot Coloring pass, possibly in instruction lowering Differential Revision: https://reviews.llvm.org/D26616 llvm-svn: 291455
* [X86][AVX512] Enable v16i8/v32i8 vector shifts to use an ↵Simon Pilgrim2017-01-097-332/+296
| | | | | | | | | | extend+shift+truncate pattern. Use the existing AVX2 v8i16 vector shift lowering for v16i8 (extending to v16i32) on AVX512 targets and v32i8 (extending to v32i16) on AVX512BW targets. Cost model updates to follow. llvm-svn: 291451
* fix comment typos; NFCSanjay Patel2017-01-092-7/+7
| | | | llvm-svn: 291447
* [X86][AVX512DQ] Enable v16i16 vector shifts to use an extend+shift+truncate ↵Simon Pilgrim2017-01-097-148/+60
| | | | | | | | | | pattern. Use the existing AVX2 v8i16 vector shift lowering for v16i16 on AVX512 targets (AVX512BW will have already have lowered with vpsravw). Cost model updates to follow. llvm-svn: 291445
* [X86][AVX512DQ] Added AVX512DQ to 128/256 bit vector shift testsSimon Pilgrim2017-01-096-84/+215
| | | | llvm-svn: 291444
* [IR] Adding const_value_op_iterator for IR/User.hMohammed Agabaria2017-01-092-0/+45
| | | | | | | | const value op iterator is missing from User.h class. Differential Revision: https://reviews.llvm.org/D28464 llvm-svn: 291443
* Some formatting in TargetMachineC. NFCAmaury Sechet2017-01-091-2/+2
| | | | llvm-svn: 291442
* [SelectionDAG] Fix in legalization of UMAX/SMAX/UMIN/SMIN. Solves PR31486.Bjorn Pettersson2017-01-092-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Originally i64 = umax t8, Constant:i64<4> was expanded into i32,i32 = umax Constant:i32<0>, Constant:i32<0> i32,i32 = umax t7, Constant:i32<4> Now instead the two produced umax:es return i32 instead of i32, i32. Thanks to Jan Vesely for help with the test case. Patch by mikael.holmen at ericsson.com Reviewers: bogner, jvesely, tstellarAMD, arsenm Subscribers: test, wdng, RKSimon, arsenm, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D28135 llvm-svn: 291441
* RuntimeDyldELF: add missing test cases for AArch64Eugene Leviant2017-01-092-3/+43
| | | | llvm-svn: 291438
* Fix MSVC build failure introduced in r291431Pavel Labath2017-01-091-4/+3
| | | | | | | MSVC does not like to reinterpret_cast to a uint64_t. Use a different cast instead. llvm-svn: 291435
* RuntimeDyldELF: don't create thunk if not neededEugene Leviant2017-01-093-1/+61
| | | | | | | | | | | | | This patch doesn't create thunk for branch operation when following conditions are met: - Architecture is AArch64 - Relocation target is in the same object file - Relocation target is close enough to be encoded in immediate offset In such case we branch directly to the target instead of branching to thunk Differential revision: https://reviews.llvm.org/D28108 llvm-svn: 291431
* [PM] Teach SCEV to invalidate itself when its dependencies becomeChandler Carruth2017-01-093-0/+84
| | | | | | | | | | | | | invalid. This fixes use-after-free bugs that will arise with any interesting use of SCEV. I've added a dedicated test that works diligently to trigger these kinds of bugs in the new pass manager and also checks for them explicitly as well as triggering ASan failures when things go squirly. llvm-svn: 291426
* [WebAssembly] Fix the opcode values for i64.eq and i64.ne.Dan Gohman2017-01-091-2/+2
| | | | llvm-svn: 291424
* Remove unused method in LoopVectorize.cpp.Jonas Paulsson2017-01-091-7/+0
| | | | | | | computeInterleaveCount() is not defined/used and is therefore removed. Review: Davide Italiano llvm-svn: 291423
* NewGVN: Fix PR 31573, a failure to verify memory congruency due toDaniel Berlin2017-01-092-1/+56
| | | | | | | not excluding ourselves when checking if any equivalent stores exist. llvm-svn: 291421
* NewGVN: Change a std::vector to SmallVector and cleanup naming.Daniel Berlin2017-01-091-10/+11
| | | | llvm-svn: 291420
* [AVX-512] Change another pattern that was using BLENDM to use masked moves. ↵Craig Topper2017-01-093-38/+47
| | | | | | A future patch will conver it back to BLENDM if its beneficial to register allocation. llvm-svn: 291419
* [AVX-512] Add patterns to use a zero masked VPTERNLOG instruction for ↵Craig Topper2017-01-0913-217/+184
| | | | | | | | vselects of all ones and all zeros. Previously we emitted a VPTERNLOG and a separate masked move. llvm-svn: 291415
* Define sys::path::convert_to_slashRui Ueyama2017-01-093-10/+20
| | | | | | | | This patch moves convertToUnixPathSeparator from LLD to LLVM. Differential Revision: https://reviews.llvm.org/D28444 llvm-svn: 291414
* CommandLine option: Relax the assertion introduced in r290467 to allows for ↵Mehdi Amini2017-01-081-1/+1
| | | | | | | | | empty string This is used in LDC for custom boolean commandline options, setArgStr is called with an empty string before using AddLiteralOption. llvm-svn: 291406
* [MemDep] NFC walk invariant.group graph only downPiotr Padlewski2017-01-083-26/+120
| | | | | | | | | | | | | | Summary: By using stripPointerCasts we can get to the root value and then walk down the bitcast graph Reviewers: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28181 llvm-svn: 291405
* [LCSSA] Fix some typos. NFCI.Davide Italiano2017-01-081-3/+3
| | | | llvm-svn: 291404
* [AVX-512] If avx512dq is available use vpmovm2d/vpmovm2q instead of vselect ↵Craig Topper2017-01-082-37/+101
| | | | | | of zeroes/ones when handling sign extends of i1 without VLX. llvm-svn: 291402
* [X86] Add avx512bw and avx512dq command lines to the vector compare results ↵Craig Topper2017-01-081-1498/+4602
| | | | | | | | test. This is preparation for improving a case with avx512dq. llvm-svn: 291401
* [SCCP] Unknown instructions are sent to overdefined anyway. NFCI.Davide Italiano2017-01-081-18/+0
| | | | llvm-svn: 291400
* [Orc][RPC] Lock the pending results data structure when installing new resultLang Hames2017-01-081-22/+51
| | | | | | | | | | | | | handlers, make abandonPendingResults public API. This should make installing asynchronous result handlers thread safe. The abandonPendingResults method is made public so that clients can disconnect from a remote even if they have asynchronous handlers awaing results from that remote. The asynchronous handlers will all receive "abandoned result" errors as their argument. llvm-svn: 291399
* llvm-objdump: speed up -objc-meta-dataSaleem Abdulrasool2017-01-082-26/+13
| | | | | | | | | | | | | | | | | | Running a Debug build of objdump -objc-meta-data with a large Mach-O file is currently unnecessarily slow. With some local test input, this change reduces the run time from 75-85s down to 15-20s. The two changes are: Assert on pointer equality not array equality Replace vector<pair<address, symbol>> with DenseMap<address, symbol> Additionally, use a std::unique_ptr rather than handling the memory manually. Patch by Dave Lee! llvm-svn: 291398
* Strip trailing whitespace.Simon Pilgrim2017-01-081-1/+1
| | | | llvm-svn: 291395
* unittest: remove extraneous ';'Saleem Abdulrasool2017-01-081-1/+1
| | | | | | Silences a warning from gcc:6. NFC llvm-svn: 291394
* Fix line endings and strip trailing whitespace.Simon Pilgrim2017-01-081-71/+71
| | | | llvm-svn: 291393
* [x86] fix usage of stale operands when lowering selectSanjay Patel2017-01-082-7/+10
| | | | | | | | | | | | | | | | | | | | | I noticed this problem as part of the ongoing attempt to canonicalize min/max ops in IR. The debug output shows nodes like this: t4: i32 = xor t2, Constant:i32<-1> t21: i8 = setcc t4, Constant:i32<0>, setlt:ch t14: i32 = select t21, t4, Constant:i32<-1> And because the select is holding onto the t4 (xor) node while EmitTest creates a new x86-specific xor node, the lowering results in: t4: i32 = xor t2, Constant:i32<-1> t25: i32,i32 = X86ISD::XOR t2, Constant:i32<-1> t28: i32,glue = X86ISD::CMOV Constant:i32<-1>, t4, Constant:i8<15>, t25:1 Differential Revision: https://reviews.llvm.org/D28374 llvm-svn: 291392
* [CostModel][X86] Fixed vXi8 uniform shift costs.Simon Pilgrim2017-01-086-45/+61
| | | | | | | | | | The 'fast' costs should only work for shifts by uniform constants (uniform non-constant are lowered using the slow default implementation). Logical shifts were not taking into account that we must mask the psrlw result, so the costs needed to be doubled. Added missing AVX2/AVX512BW costs as well. llvm-svn: 291391
* [CostModel][X86] Moved legal uniform shift costs earlier.Simon Pilgrim2017-01-083-32/+44
| | | | | | XOP was prematurely matching, doubling the cost of ashr/lshr uniform shifts. llvm-svn: 291390
* [AVX-512] Remove redundant patterns that select unaligned moves with zero ↵Craig Topper2017-01-081-1/+1
| | | | | | masking for patterns that already use the aligned form. NFC llvm-svn: 291383
* [Orc][RPC] Fix typo.Lang Hames2017-01-081-1/+1
| | | | llvm-svn: 291381
* [Orc][RPC] Add an APICalls utility for grouping RPC funtions for registration.Lang Hames2017-01-082-32/+150
| | | | | | | | | | | | | APICalls allows groups of functions to be composed into an API that can be registered as a unit with an RPC endpoint. Doing registration on a-whole API basis (rather than per-function) allows missing API functions to be detected early. APICalls also allows Function membership to be tested at compile-time. This allows clients to write static assertions that functions to be called are members of registered APIs. llvm-svn: 291380
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