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* Duncan owns dragonegg too, it's all his fault :)Chris Lattner2011-09-231-1/+1
| | | | llvm-svn: 140430
* Verify that terminators follow non-terminators.Jakob Stoklund Olesen2011-09-232-0/+16
| | | | | | This exposes a -segmented-stacks bug. llvm-svn: 140429
* PR10998: It is not legal to sink an instruction past the terminator of a ↵Eli Friedman2011-09-232-1/+52
| | | | | | block; make sure we don't do that. llvm-svn: 140428
* Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset ↵Owen Anderson2011-09-232-1/+3
| | | | | | of #-0. llvm-svn: 140426
* Also match negative offsets for addrmode3 and addrmode5.Jakob Stoklund Olesen2011-09-232-2/+20
| | | | | | | | Math is hard, and isScaledConstantInRange() always returned false for negative constants. It was doing unsigned division of negative numbers before casting back to signed. llvm-svn: 140425
* Fix incorrect disassembly test.Owen Anderson2011-09-231-1/+1
| | | | llvm-svn: 140423
* Add more fixed bits to USAT16 encoding to filter out incorrect decodings.Owen Anderson2011-09-231-2/+2
| | | | llvm-svn: 140422
* Post-index loads/stores in still need to print the post-indexed immediate, ↵Owen Anderson2011-09-233-11/+18
| | | | | | even if it's zero, to distinguish them from non-post-indexed instructions. llvm-svn: 140420
* Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid ↵Owen Anderson2011-09-232-3/+3
| | | | | | testcases updated. llvm-svn: 140415
* Revert r140412. This affects more instructions than intended.Owen Anderson2011-09-231-1/+1
| | | | llvm-svn: 140413
* Thumb2 register-shifted-register loads cannot target the PC or the SP.Owen Anderson2011-09-231-1/+1
| | | | llvm-svn: 140412
* Add getTreeFactory() to ImmutableSet to allow construction of ↵Anna Zaks2011-09-231-0/+4
| | | | | | ImmutableSetRef from an ImmutableSet object. llvm-svn: 140402
* Implement N32/64 calling convention. Patch by Liu.Akira Hatanaka2011-09-231-1/+54
| | | | llvm-svn: 140401
* Make FGR64RegisterClass available if target is Mips64.Akira Hatanaka2011-09-231-1/+6
| | | | llvm-svn: 140397
* Add definitions of 64-bit register files. Add code for returning Mips64's ↵Akira Hatanaka2011-09-232-9/+81
| | | | | | | | sets of callee-saved registers and reserved registers. llvm-svn: 140395
* PTX: Fix parameter order bugJustin Holewinski2011-09-232-8/+8
| | | | llvm-svn: 140394
* Fix a couple of 80 column violations.Wesley Peck2011-09-232-2/+3
| | | | | | patch contributed by Jia Liu! llvm-svn: 140391
* PTX: Cleanup unused code in PTXMachineFunctionInfoJustin Holewinski2011-09-233-158/+60
| | | | llvm-svn: 140390
* PTX: Fix another 80-column violationJustin Holewinski2011-09-231-1/+2
| | | | llvm-svn: 140387
* PTX: Handle function call return valuesJustin Holewinski2011-09-233-18/+68
| | | | llvm-svn: 140386
* Fix 80 column violations.Richard Osborne2011-09-233-8/+16
| | | | | | Original patch by Liu. llvm-svn: 140385
* Implement Chris's suggestion of legalizing the various SSE and AVXDuncan Sands2011-09-232-64/+13
| | | | | | hadd/hsub intrinsics into the new fhadd/fhsub X86 node. llvm-svn: 140383
* Modified demo to use 3.0 resume instruction vs calling _Unwine_Resume.Garrison Venn2011-09-231-93/+116
| | | | | | | | | | | | | | Also conducted some reformatting. As the LLVM coding standard doc does not seem to touch on how to align function arguments, and format code longer than 80 cols in general, the confusion persists. There is the golden rule, but as this code has gone through several styles to deal with this, the golden rule seems to be ignored. The latest reformatting effort tries to match the other source files as much as possible. Tested on OS X 10.7.1 with, and without the OLD_EXC_SYSTEM defined. Have NOT tested on LINUX. llvm-svn: 140379
* PTX: Start fixing function callsJustin Holewinski2011-09-233-4/+16
| | | | llvm-svn: 140378
* PTX: Remove PTX calling convention filesJustin Holewinski2011-09-232-192/+0
| | | | llvm-svn: 140377
* [PATCH 2/2] PTXInstrInfo.td PTXIntrinsicInstrInfo.td 80 columnsJustin Holewinski2011-09-232-81/+162
| | | | | | | | | | From 5936c03172e251f12a0332d1033de5718e6e2091 Mon Sep 17 00:00:00 2001 --- lib/Target/PTX/PTXInstrInfo.td | 165 ++++++++++++++++++++---------- lib/Target/PTX/PTXIntrinsicInstrInfo.td | 88 +++++++++++------ 2 files changed, 167 insertions(+), 86 deletions(-) llvm-svn: 140376
* PTX: Generalize handling of .param typesJustin Holewinski2011-09-237-22/+204
| | | | llvm-svn: 140375
* PTX: Cleanup unused code in the PTXMFInfoExtract passJustin Holewinski2011-09-231-31/+0
| | | | llvm-svn: 140374
* Tweak the handling of MERGE_VALUES nodes: remove the need forDuncan Sands2011-09-236-51/+43
| | | | | | | | | DecomposeMERGE_VALUES to "know" that results are legalized in a particular order, by passing it the number of the result being legalized (the type legalization core provides this, it just needs to be passed on). llvm-svn: 140373
* Vector-Select: Address one of the problems in pr10902. Add handling for theNadav Rotem2011-09-232-0/+43
| | | | | | | | | | integer-promotion of CONCAT_VECTORS. Test: test/CodeGen/X86/widen_shuffle-1.ll This patch fixes the above tests (when running in with -promote-elements). llvm-svn: 140372
* Don't allow 32-bit only instructions to be disassembled in 64-bit mode. ↵Craig Topper2011-09-235-13/+23
| | | | | | Fixes part of PR10700. llvm-svn: 140370
* Add definitions of 64-bit int registers.Akira Hatanaka2011-09-231-0/+41
| | | | llvm-svn: 140366
* Do not rely on the enum values of argument registers A0-A3 being consecutive.Akira Hatanaka2011-09-231-3/+11
| | | | | | | | Define function getNextIntArgReg, which takes a register as a parameter and returns the next O32 argument integer register. Use this function when double precision floating point arguments are passed in two integer registers. llvm-svn: 140363
* We're no longer going to bother supporting platforms that don'tEric Christopher2011-09-234-201/+2
| | | | | | | | support C89. We probably didn't support them anyways. llvm-svn: 140361
* PR10989: Don't print .hidden on Windows.Eli Friedman2011-09-232-7/+15
| | | | llvm-svn: 140356
* PR10991: make fast-isel correctly check whether accessing a global through ↵Eli Friedman2011-09-222-2/+28
| | | | | | an alias involves thread-local storage. (I'm not entirely sure how this is supposed to work, but this patch makes fast-isel consistent with the normal isel path.) llvm-svn: 140355
* Make changes in instruction and pattern definitions so that tablegen does notAkira Hatanaka2011-09-222-27/+27
| | | | | | | complain it cannot infer types in patterns. Fix a mistake in definition of SDT_MipsExtractElementF64. llvm-svn: 140354
* Add new files to CMake.Owen Anderson2011-09-221-0/+2
| | | | llvm-svn: 140352
* Fix SimplifySelectCC to add newly created nodes to the DAGCombinerDan Gohman2011-09-222-6/+9
| | | | | | worklist, as it may be possible to perform further optimization on them. llvm-svn: 140349
* Add support for GR32 <-> FR32 cross class copies.Jakob Stoklund Olesen2011-09-221-0/+11
| | | | | | | | We already support GR64 <-> VR128 copies. All of these copies break partial register dependencies by zeroing the high part of the target register. llvm-svn: 140348
* Update CMake build.Benjamin Kramer2011-09-221-0/+2
| | | | llvm-svn: 140347
* Start stubbing out MCModule and MCAtom, which provide an API for accessing ↵Owen Anderson2011-09-224-0/+257
| | | | | | | | the rich disassembly of a complete object or executable. These are very much a work in progress, and not really useful yet. llvm-svn: 140345
* Constrain register classes instead of emitting copies.Jakob Stoklund Olesen2011-09-221-3/+5
| | | | | | | | | | | Sometimes register class constraints are trivial, like GR32->GR32_NOSP, or GPR->rGPR. Teach InstrEmitter to simply constrain the virtual register instead of emitting a copy in these cases. Normally, these copies are handled by the coalescer. This saves some coalescer work. llvm-svn: 140340
* Add a MinNumRegs argument to MRI::constrainRegClass().Jakob Stoklund Olesen2011-09-222-7/+11
| | | | | | | | | | | The function will refuse to use a register class with fewer registers than MinNumRegs. This can be used by clients to avoid accidentally increase register pressure too much. The default value of MinNumRegs=0 doesn't affect how constrainRegClass() works. llvm-svn: 140339
* Synthesize SSE3/AVX 128 bit horizontal add/sub instructions fromDuncan Sands2011-09-225-22/+434
| | | | | | | floating point add/sub of appropriate shuffle vectors. Does not synthesize the 256 bit AVX versions because they work differently. llvm-svn: 140332
* PR10987: add a missed safety check to isSafePHIToSpeculate in scalarrepl.Eli Friedman2011-09-222-7/+51
| | | | llvm-svn: 140327
* Resynch intro to section with copyright section.Chris Lattner2011-09-221-2/+3
| | | | llvm-svn: 140326
* Print parentheses in next line.Akira Hatanaka2011-09-221-2/+4
| | | | llvm-svn: 140325
* Change subreg index of AFPR64 from sub_fpeven to sub_32 per Jakob's comment.Akira Hatanaka2011-09-221-1/+1
| | | | llvm-svn: 140324
* Define a new sub-register index sub_32 for accessing the 32-bit sub-register ofAkira Hatanaka2011-09-221-4/+5
| | | | | | | a 64-bit integer register. Move the subreg index definitions to the beginning of the file. llvm-svn: 140319
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