summaryrefslogtreecommitdiffstats
path: root/llvm
Commit message (Collapse)AuthorAgeFilesLines
* [Orc] It's not valid to pass a null resolver to addModuleSet. Use a no-opLang Hames2015-04-291-4/+19
| | | | | | resolver with a diagnostic instread. llvm-svn: 236074
* Make sure that isValidElementType(Type) before calling ↵Filipe Cabecinhas2015-04-294-2/+11
| | | | | | | | {Array,Struct}Type::get(Type) Bug found with AFL fuzz. llvm-svn: 236073
* RegisterCoalescer: hide terminal rule option by defaultMatthias Braun2015-04-281-1/+1
| | | | llvm-svn: 236062
* test-release.sh: Drop some unused command-line options.Hans Wennborg2015-04-281-12/+0
| | | | | | These haven't done anything since before r142165. llvm-svn: 236061
* Map directly from signature symbol to group index. NFC.Rafael Espindola2015-04-281-10/+13
| | | | llvm-svn: 236058
* Reuse a lookup in an assert.Eric Christopher2015-04-281-3/+3
| | | | llvm-svn: 236054
* Remove redundant temporary std::vector.Rafael Espindola2015-04-281-25/+7
| | | | | | | New sections are added to the end of the list, so the RelSections array was redundant. llvm-svn: 236053
* ARM: fix peephole optimisation of TSTTim Northover2015-04-282-16/+28
| | | | | | | | | | | We were trying to look through COPY instructions, but only to the next instruction in a BB and incorrectly anyway. The cases where that would actually be a good idea are rare enough (and not even tested!) that it's not worth trying to get right. rdar://20721342 llvm-svn: 236050
* Avoid one more walk over all sections. NFC.Rafael Espindola2015-04-281-9/+3
| | | | | | Set the group section index as they are created. llvm-svn: 236049
* Style updatesAndrew Kaylor2015-04-281-18/+19
| | | | llvm-svn: 236048
* Use a range loop. NFC.Rafael Espindola2015-04-281-3/+2
| | | | llvm-svn: 236047
* [WinEH] Split blocks at calls to llvm.eh.begincatchAndrew Kaylor2015-04-286-36/+206
| | | | | | Differential Revision: http://reviews.llvm.org/D9311 llvm-svn: 236046
* Avoid an extra walk over the sections just to assign sections to groups.Rafael Espindola2015-04-281-30/+41
| | | | | | Assign the sections in the same pass we compute the index. llvm-svn: 236045
* Sparc: Add alternate aliases for conditional branch instructions.James Y Knight2015-04-282-0/+30
| | | | llvm-svn: 236042
* [SEH] Add an LLVM intrinsic for _exception_infoReid Kleckner2015-04-281-0/+1
| | | | | | Eventually, we will lower this out during IR preparation. llvm-svn: 236036
* Remove the GroupMapTy DenseMap. NFC.Rafael Espindola2015-04-283-21/+13
| | | | | | Instead use the Group symbol of MCSectionELF. llvm-svn: 236033
* transform fadd chains to increase parallelismSanjay Patel2015-04-282-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a compromise: with this simple patch, we should always handle a chain of exactly 3 operations optimally, but we're not generating the optimal balanced binary tree for a longer sequence. In general, this transform will reduce the dependency chain for a sequence of instructions using N operands from a worst case N-1 dependent operations to N/2 dependent operations. The optimal balanced binary tree would reduce the chain to log2(N). The trade-off for not dealing with longer sequences is: (1) we have less complexity in the compiler, (2) we avoid unknown compile-time blowup calculating a balanced tree, and (3) we don't need to worry about the increased register pressure required to parallelize longer sequences. It also seems unlikely that we would ever encounter really long strings of dependent ops like that in the wild, but I'm not sure how to verify that speculation. FWIW, I see no perf difference for test-suite running on btver2 (x86-64) with -ffast-math and this patch. We can extend this patch to cover other associative operations such as fmul, fmax, fmin, integer add, integer mul. This is a partial fix for: https://llvm.org/bugs/show_bug.cgi?id=17305 and if extended: https://llvm.org/bugs/show_bug.cgi?id=21768 https://llvm.org/bugs/show_bug.cgi?id=23116 The issue also came up in: http://reviews.llvm.org/D8941 Differential Revision: http://reviews.llvm.org/D9232 llvm-svn: 236031
* [bpf] fix buildAlexei Starovoitov2015-04-282-8/+9
| | | | | | Patch by Brenden Blanco. llvm-svn: 236030
* Use range loops. NFC.Rafael Espindola2015-04-281-7/+3
| | | | llvm-svn: 236028
* Relax an assert when there's a type mismatch in forward referencesFilipe Cabecinhas2015-04-283-1/+8
| | | | | | | | | | | | | | | | Summary: We don't seem to need to assert here, since this function's callers expect to get a nullptr on error. This way we don't assert on user input. Bug found with AFL fuzz. Reviewers: rafael Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9308 llvm-svn: 236027
* Avoid adding to SectionIndexMap sections that we never lookup. NFC.Rafael Espindola2015-04-281-33/+28
| | | | llvm-svn: 236026
* Make getModRefInfo(Instruction *) not crash on certain types of instructionsDaniel Berlin2015-04-282-10/+23
| | | | llvm-svn: 236023
* Use a range loop. NFC.Rafael Espindola2015-04-281-3/+2
| | | | llvm-svn: 236015
* [x86] remove RCPPS and RSQRTPS intrinsic instruction definitionsSanjay Patel2015-04-283-52/+6
| | | | | | | | | | | | | We don't need codegen-only intrinsic instructions for the vector forms of these instructions. This makes the reciprocal estimate instruction lowering identical to how we handle normal square roots: (V)SQRTPS / (V)SQRTPD. No existing regression tests fail with this patch. Differential Revision: http://reviews.llvm.org/D9301 llvm-svn: 236013
* Add a fixme to resetTargetOptions to explain why it needs to goEric Christopher2015-04-281-0/+5
| | | | | | away. llvm-svn: 236009
* Fix a [-Werror,-Winconsistent-missing-override] problem in theEric Christopher2015-04-281-1/+1
| | | | | | NVPTX overrides. llvm-svn: 236007
* R600: Fix up for AsmPrinter's OutStreamer being a unique_ptrTom Stellard2015-04-282-2/+13
| | | | | | | | | | | Fixes a crash with basically any OpenGL application using the radeonsi driver. Patch by: Michel Dänzer Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90176 Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 236004
* R600/SI: Add a lower case alias for subtarget feature: +DumpCodeTom Stellard2015-04-281-0/+5
| | | | | | | llc converts all feature strings to lower case, while the LLVM C API does not, so we need a lower case alias in order to test this with llc. llvm-svn: 236003
* [NVPTX] Handle addrspacecast constant expressions in aggregate initializersJustin Holewinski2015-04-285-2/+270
| | | | | | | | | | | We need to track if an AddrSpaceCast expression was seen when generating an MCExpr for a ConstantExpr. This change introduces a custom lowerConstant method to the NVPTX asm printer that will create NVPTXGenericMCSymbolRefExpr nodes at the appropriate places to encode the information that a given symbol needs to be casted to a generic address. llvm-svn: 236000
* [opaque pointer type] Encode the allocated type of an alloca rather than its ↵David Blaikie2015-04-282-8/+16
| | | | | | pointer result type. llvm-svn: 235998
* move IR-level optimization flags into their own structSanjay Patel2015-04-284-27/+70
| | | | | | | | | | | | | | | | | | | | | | This is a preliminary step to using the IR-level floating-point fast-math-flags in the SDAG (D8900). In this patch, we introduce the optimization flags as their own struct. As noted in the TODO comment, we should eventually share this data between the IR passes and the backend. We also switch the existing nsw / nuw / exact bit functionality of the BinaryWithFlagsSDNode class to use the new struct. The tradeoff is that instead of using the free but limited space of SDNode's SubclassData, we add a data member to the subclass. This means we don't have to repeat all of the get/set methods per flag, but we're potentially adding size to all nodes of this subclassi type. In practice on 64-bit systems (measured on Linux and MacOS X), there is no size difference between an SDNode and BinaryWithFlagsSDNode after this change: they're both 80 bytes. This means that we had at least one free byte to play with due to struct alignment. Differential Revision: http://reviews.llvm.org/D9325 llvm-svn: 235997
* Use a std::vector to record the offsets of the sections. NFC.Rafael Espindola2015-04-281-10/+8
| | | | llvm-svn: 235995
* Avoid an extra loop for computing the section size. NFC.Rafael Espindola2015-04-281-29/+13
| | | | llvm-svn: 235994
* Fixed crash of variable shift inst on AVX2Elena Demikhovsky2015-04-282-3/+39
| | | | | | https://llvm.org/bugs/show_bug.cgi?id=22955 llvm-svn: 235993
* [mips] [IAS] Do not generate redundant ORi in createLShiftOri.Toma Tabacu2015-04-283-13/+20
| | | | | | | | | | | | | | Summary: If the immediate is 0, the ORi is pointless. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8969 llvm-svn: 235990
* Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes"Sergey Dmitrouk2015-04-2878-3705/+4400
| | | | | | | | | | | | | | | | | | | | | | | | | [DebugInfo] Add debug locations to constant SD nodes This adds debug location to constant nodes of Selection DAG and updates all places that create constants to pass debug locations (see PR13269). Can't guarantee that all locations are correct, but in a lot of cases choice is obvious, so most of them should be. At least all tests pass. Tests for these changes do not cover everything, instead just check it for SDNodes, ARM and AArch64 where it's easy to get incorrect locations on constants. This is not complete fix as FastISel contains workaround for wrong debug locations, which drops locations from instructions on processing constants, but there isn't currently a way to use debug locations from constants there as llvm::Constant doesn't cache it (yet). Although this is a bit different issue, not directly related to these changes. Differential Revision: http://reviews.llvm.org/D9084 llvm-svn: 235989
* Use CIE version 4 for dwarf4.Rafael Espindola2015-04-283-11/+26
| | | | | | | According to http://www.dwarfstd.org/doc/DWARF4.pdf appendix F the CIE version for dwarf 4 is 4. llvm-svn: 235988
* Revert "[DebugInfo] Add debug locations to constant SD nodes"Daniel Jasper2015-04-2878-4399/+3705
| | | | | | | This breaks a test: http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/23870 llvm-svn: 235987
* [mips] [IAS] Rename the createShiftOr function to createLShiftOri. NFC.Toma Tabacu2015-04-281-13/+13
| | | | | | | | | | | | | | Summary: The new name is more accurate with regard to the functionality. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8968 llvm-svn: 235984
* [mips] [IAS] Store the expandLoadImm destination register in a variable. NFC.Toma Tabacu2015-04-281-11/+12
| | | | | | | | | | | | | | Summary: This removes multiple calls to getReg() and saves us column space in the source file. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8924 llvm-svn: 235978
* [DebugInfo] Add debug locations to constant SD nodesSergey Dmitrouk2015-04-2878-3705/+4399
| | | | | | | | | | | | | | | | | | | | | | | This adds debug location to constant nodes of Selection DAG and updates all places that create constants to pass debug locations (see PR13269). Can't guarantee that all locations are correct, but in a lot of cases choice is obvious, so most of them should be. At least all tests pass. Tests for these changes do not cover everything, instead just check it for SDNodes, ARM and AArch64 where it's easy to get incorrect locations on constants. This is not complete fix as FastISel contains workaround for wrong debug locations, which drops locations from instructions on processing constants, but there isn't currently a way to use debug locations from constants there as llvm::Constant doesn't cache it (yet). Although this is a bit different issue, not directly related to these changes. Differential Revision: http://reviews.llvm.org/D9084 llvm-svn: 235977
* AVX-512: Added "pandn" intrinsics setElena Demikhovsky2015-04-283-1/+333
| | | | | | by Asaf Badouh (asaf.badouh@intel.com) llvm-svn: 235971
* Masked gather and scatter: Added code for SelectionDAG.Elena Demikhovsky2015-04-286-2/+294
| | | | | | | | All other patches, including tests will follow. http://reviews.llvm.org/D7665 llvm-svn: 235970
* [opaque pointer type] Encode the pointee type in the bitcode for 'cmpxchg'David Blaikie2015-04-285-7/+25
| | | | | | | | | | | | | | | | | As a space optimization, this instruction would just encode the pointer type of the first operand and use the knowledge that the second and third operands would be of the pointee type of the first. When typed pointers go away, this assumption will no longer be available - so encode the type of the second operand explicitly and rely on that for the third. Test case added to demonstrate the backwards compatibility concern, which only comes up when the definition of the second operand comes after the use (hence the weird basic block sequence) - at which point the type needs to be explicitly encoded in the bitcode and the record length changes to accommodate this. llvm-svn: 235966
* [MC] Use LShr for constant evaluation of ">>" on ELF/arm64--darwin.Ahmed Bougacha2015-04-288-3/+37
| | | | | | | | | | This matches other assemblers and is less unexpected (e.g. PR23227). On ELF, I tried binutils gas v2.24 and nasm 2.10.09, and they both agree on LShr. On COFF, I couldn't get my hands on an assembler yet, so don't change the behavior. For now, don't change it on non-AArch64 Darwin either, as the other assembler is gas v1.38, which does an AShr. llvm-svn: 235963
* DebugInfo: Support up to 2^16 arguments in a subprogramDuncan P. N. Exon Smith2015-04-282-5/+22
| | | | | | | | | Support up to 2^16 arguments to a function. If we do hit the limit, assert out rather than restarting at 0 as we've done historically. This fixes PR23332. A clang test will follow. llvm-svn: 235955
* Cleanup, remove unused return valueMatthias Braun2015-04-282-6/+3
| | | | llvm-svn: 235952
* [MC] Split MCBinaryExpr::Shr into LShr and AShr.Ahmed Bougacha2015-04-285-9/+23
| | | | | | | | Defaulting to AShr without consulting the target MCAsmInfo isn't OK. Add a flag to fix that. Keep it off for now: target migrations will follow in separate commits. llvm-svn: 235951
* [MC] Move getBinOpPrecedence into AsmParser. NFC.Ahmed Bougacha2015-04-281-2/+5
| | | | | | In preparation for a future patch. llvm-svn: 235950
* Switch lowering: use uint32_t for weights everywhereHans Wennborg2015-04-272-6/+12
| | | | | | | | | I previously thought switch clusters would need to use uint64_t in case the weights of multiple cases overflowed a 32-bit int. It turns out that the weights on a terminator instruction are capped to allow for being added together, so using a uint32_t should be safe. llvm-svn: 235945
OpenPOWER on IntegriCloud