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* ARM64: print fp immediates without using scientific notation.Tim Northover2014-04-309-30/+28
| | | | llvm-svn: 207669
* AArch64/ARM64: implement remaining TLS relocations (purely MC).Tim Northover2014-04-306-158/+343
| | | | llvm-svn: 207668
* AArch64/ARM64: add specific diagnostic for MRS/MSR and enable tests.Tim Northover2014-04-307-495/+508
| | | | llvm-svn: 207667
* AArch64/ARM64: accept and print floating-point immediate 0 as "#0.0"Tim Northover2014-04-305-59/+83
| | | | | | | | | | It's been decided that in the future, the floating-point immediate in instructions like "fcmeq v0.2s, v1.2s, #0.0" will be canonically "0.0", which has been implemented on AArch64 already but not ARM64. This fixes that issue. llvm-svn: 207666
* IR: Alloca clones should remember inalloca stateDavid Majnemer2014-04-301-3/+4
| | | | | | | | | Pretty straightforward, we weren't propagating whether or not an AllocaInst had 'inalloca' marked on it when it came time to clone it. The inliner exposed this bug. A reduced testcase is forthcoming. llvm-svn: 207665
* [mips] Add instruction alias (dsll and dsrl).Matheus Almeida2014-04-306-0/+14
| | | | | | | | | | | | | | Summary: The pattern dsll/dsrl $rd, $rt, $rs is found in handwritten assembly which is just a shorthand version of dsllv/dsrlv $rd, $rt, $rs. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3486 llvm-svn: 207664
* Fix a use of uninitialized memory in SmallVector's move-assignment operator.Douglas Gregor2014-04-302-10/+55
| | | | | | | | When we were moving from a larger vector to a smaller one but didn't need to re-allocate, we would move-assign over uninitialized memory in the target, then move-construct that same data again. llvm-svn: 207663
* Relax the test a bit.Rafael Espindola2014-04-301-24/+24
| | | | | | | It is not relevant where the symbol and section names are stored, just their values. llvm-svn: 207662
* R600/SI: Use VALU instructions for copying i1 valuesTom Stellard2014-04-3010-9/+188
| | | | | | | | | We can't use SALU instructions for this since they ignore the EXEC mask and are always executed. This fixes several OpenCV tests. llvm-svn: 207661
* R600/SI: Teach moveToVALU how to handle some SMRD instructionsTom Stellard2014-04-303-1/+77
| | | | llvm-svn: 207660
* [ARM64][fast-isel] Fast-isel doesn't know how to handle f128.Chad Rosier2014-04-302-2/+47
| | | | llvm-svn: 207659
* Rename the test, it is testing the symver directive.Rafael Espindola2014-04-301-0/+0
| | | | llvm-svn: 207658
* [mips] Add instruction alias (sll and srl).Matheus Almeida2014-04-3010-0/+22
| | | | | | | | | | | | | | Summary: The pattern sll/srl $rd, $rt, $rs is found in handwritten assembly which is just a shorthand version of sllv/srlv $rd, $rt, $rs. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3483 llvm-svn: 207657
* [mips] Fix MipsLongBranch pass to work when the offset from the branch to theSasa Stankovic2014-04-3010-16501/+296
| | | | | | | | | | | | | | target cannot be determined accurately. This is the case for NaCl where the sandboxing instructions are added in MC layer, after the MipsLongBranch pass. It is also the case when the code has inline assembly. Instead of calculating offset in the MipsLongBranch pass, use %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions that are resolved during the fixup. This patch also deletes microMIPS test file test/CodeGen/Mips/micromips-long-branch.ll and implements microMIPS CHECKs in a much simpler way in a file test/CodeGen/Mips/longbranch.ll, together with MIPS32 and MIPS64. llvm-svn: 207656
* [mips] Update tests with encoding information for slt, slti, sltiu and sltu.Matheus Almeida2014-04-309-36/+36
| | | | | | | | | | | | | | Summary: Also renamed non-portable register names (e.g. $t2) so that we don't end up with a different encoding for what appears to be an equivalent instruction. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3505 llvm-svn: 207655
* R600: Remove unused function AMDGPUSubtarget::getDefaultSize()Tom Stellard2014-04-302-13/+0
| | | | llvm-svn: 207654
* [asan] Disable asm instrumentation on unsupported platforms.Evgeniy Stepanov2014-04-301-3/+6
| | | | | | | | | Only emit calls to compiler-rt asm routines on platforms where they are present (currently limited to linux i386/x86_64). Patch by Yuri Gorshenin. llvm-svn: 207651
* ARM64: enable AArch64's basic-a64-instructions testTim Northover2014-04-301-889/+1093
| | | | llvm-svn: 207650
* ARM64: print lsr instead of lsrv for variable shifts (etc)Tim Northover2014-04-304-39/+39
| | | | | | | The canonical syntax for shifts by a variable amount does not end with 'v', but that syntax should be supported as an alias (presumably for legacy reasons). llvm-svn: 207649
* ARM64: use 32-bit operations for uxtb & uxthTim Northover2014-04-302-5/+21
| | | | | | Testing will be enabled shortly with basic-a64-instructions.s llvm-svn: 207648
* AArch64/ARM64: allow smaller granule relocations on MOVZ/MOVNTim Northover2014-04-301-6/+6
| | | | | | Testing will be enabled shortly with basic-a64-instructions.s llvm-svn: 207647
* AArch64/ARM64: copy support for bCC instead of b.CC across.Tim Northover2014-04-302-0/+58
| | | | llvm-svn: 207646
* AArch64/ARM64: expunge CPSR from the sourcesTim Northover2014-04-3012-123/+125
| | | | | | | | | | | | AArch64 does not have a CPSR register in the same way that AArch32 does. Most of its compiler-relevant roles have been taken over by the more specific NZCV register (representing just the flags set by normal instructions). Its system control functions still remain, but are now under the pseudo-register referred to as "PSTATE". They're accessed via various MRS & MSR instructions described in the reference manual. llvm-svn: 207645
* AArch64/ARM64: use HS instead of CS & LO instead of CC.Tim Northover2014-04-309-44/+44
| | | | | | | | | On instructions using the NZCV register, a couple of conditions have dual representations: HS/CS and LO/CC (meaning unsigned-higher-or-same/carry-set and unsigned-lower/carry-clear). The first of these is more descriptive in most circumstances, so we should print it. llvm-svn: 207644
* Grammar fix.Rafael Espindola2014-04-301-1/+1
| | | | | | Thanks to Saleem Abdulrasool for noticing it. llvm-svn: 207643
* [mips][msa] Fix vector insertions where the index is variableDaniel Sanders2014-04-305-0/+347
| | | | | | | | | | | | | | | | | | | | | Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 llvm-svn: 207640
* ARM64: accept ELF-relocated load/store insts without a #.Tim Northover2014-04-302-21/+22
| | | | | | | E.g. we print "ldr x0, [x0, :lo12:symbol]" so we need to accept that syntax too. llvm-svn: 207639
* ARM64: remove duplication by templating InstPrinter methodsTim Northover2014-04-304-215/+65
| | | | | | No functional change, so no tests. llvm-svn: 207638
* [mips] Add support for .cpload.Matheus Almeida2014-04-305-0/+148
| | | | | | | | | | | | | | | | | | | | Summary: This directive is used for setting up $gp in the beginning of a function. It expands to three instructions if PIC is enabled: lui $gp, %hi(_gp_disp) addui $gp, $gp, %lo(_gp_disp) addu $gp, $gp, $reg _gp_disp is a special symbol that the linker sets to the distance between the lui instruction and the context pointer (_gp). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3480 llvm-svn: 207637
* [mips] Emit all three relocation operations for each relocation entry on ↵Matheus Almeida2014-04-303-1/+16
| | | | | | | | | | | | | | | | Mips64 big-endian systems. Summary: The N64 ABI allows up to three operations to be specified per relocation record independently of the endianness. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3529 llvm-svn: 207636
* ARM64: use hex immediates for movz/movk instructionsTim Northover2014-04-3020-149/+150
| | | | | | | | Since these are mostly used in "lsl #16", "lsl #32", "lsl #48" combinations to piece together an immediate in 16-bit chunks, hex is probably the most appropriate format. llvm-svn: 207635
* ARM64: hexify printing various immediate operandsTim Northover2014-04-3014-158/+167
| | | | | | | | | | This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. llvm-svn: 207634
* ARM64: print canonical syntax for add/sub (imm) instructions.Tim Northover2014-04-3012-54/+56
| | | | | | | | | | Since these instructions only accept a 12-bit immediate, possibly shifted left by 12, the canonical syntax used by the architecture reference manual is "#N {, lsl #12 }". We should accept an immediate that has already been shifted, (e.g. Also, print a comment giving the full addend since it can be helpful. llvm-svn: 207633
* [LCG] Add the really, *really* boring edge insertion case: adding anChandler Carruth2014-04-303-4/+74
| | | | | | | | | | edge entirely within an existing SCC. Shockingly, making the connected component more connected is ... a total snooze fest. =] Anyways, its wired up, and I even added a test case to make sure it pretty much sorta works. =D llvm-svn: 207631
* Fix multiline comment warning.Evgeniy Stepanov2014-04-301-11/+11
| | | | | | | | ../unittests/Analysis/LazyCallGraphTest.cpp:45:1: warning: multi-line comment [-Wcomment] // / \ ^ llvm-svn: 207629
* [ARM64] Simplify if condition.James Molloy2014-04-301-6/+2
| | | | | | | v2f32 and v4f32 were missed out of these conditions, so this is also a bugfix. llvm-svn: 207628
* [ARM64] Fix stupid copy-pasto in ARM64MCAsmInfo.cpp - aarch64_be -> arm64_beJames Molloy2014-04-301-1/+1
| | | | llvm-svn: 207627
* [ARM64] Try and make the ELF MCJIT *slightly* less broken for ARM64.James Molloy2014-04-303-3/+11
| | | | | | | | | A bunch of switch cases were missing, not just for ARM64 but also for AArch64_BE. I've fixed all those, but there's zero testing as ExecutionEngine tests are disabled when crosscompiling and I don't have a native platform available to test on. llvm-svn: 207626
* [ARM64] Ensure arm64_be is dealt with when emitting debug info.James Molloy2014-04-302-1/+3
| | | | | | | This is a partial port of r204816 (cpirker "Elf support for MC-JIT runtime dynamic linker") from AArch64 to ARM64. llvm-svn: 207625
* raw_ostream::operator<<(StringRef): Avoid potential overflow in pointer ↵NAKAMURA Takumi2014-04-301-1/+1
| | | | | | | | | | | | | | arithmetic. (OutBufCur + Size) might overflow if Size were large. For example on i686-linux, OutBufCur: 0xFFFDF27D OutBufEnd: 0xFFFDF370 Size: 0x0002BF20 (180,000) It caused flaky error in MC/COFF/section-name-encoding.s. llvm-svn: 207621
* ARM64: make sure FastISel uses a GPR64 source in 64-bit extensions.Tim Northover2014-04-302-8/+43
| | | | llvm-svn: 207620
* [LCG] Actually test the *basic* edge removal bits (IE, the non-SCCChandler Carruth2014-04-303-7/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | bits), and discover that it's totally broken. Yay tests. Boo bug. Fix the basic edge removal so that it works by nulling out the removed edges rather than actually removing them. This leaves the indices valid in the map from callee to index, and preserves some of the locality for iterating over edges. The iterator is made bidirectional to reflect that it now has to skip over null entries, and the skipping logic is layered onto it. As future work, I would like to track essentially the "load factor" of the edge list, and when it falls below a threshold do a compaction. An alternative I considered (and continue to consider) is storing the callees in a doubly linked list where each element of the list is in a set (which is essentially the classical linked-hash-table datastructure). The problem with that approach is that either you need to heap allocate the linked list nodes and use pointers to them, or use a bucket hash table (with even *more* linked list pointer overhead!), etc. It's pretty easy to get 5x overhead for values that are just pointers. So far, I think punching holes in the vector, and periodic compaction is likely to be much more efficient overall in the space/time tradeoff. llvm-svn: 207619
* Add a <tuple> include to more files that aren't getting it transitively on MSVC.Benjamin Kramer2014-04-302-0/+2
| | | | llvm-svn: 207617
* Use makeArrayRef insted of calling ArrayRef<T> constructor directly. I ↵Craig Topper2014-04-3013-44/+37
| | | | | | introduced most of these recently. llvm-svn: 207616
* ARM: support stack probe emission for Windows on ARMSaleem Abdulrasool2014-04-303-4/+114
| | | | | | | | | | | | | | | | | This introduces the stack lowering emission of the stack probe function for Windows on ARM. The stack on Windows on ARM is a dynamically paged stack where any page allocation which crosses a page boundary of the following guard page will cause a page fault. This page fault must be handled by the kernel to ensure that the page is faulted in. If this does not occur and a write access any memory beyond that, the page fault will go unserviced, resulting in an abnormal program termination. The watermark for the stack probe appears to be at 4080 bytes (for accommodating the stack guard canaries and stack alignment) when SSP is enabled. Otherwise, the stack probe is emitted on the page size boundary of 4096 bytes. llvm-svn: 207615
* ConstantHoisting.cpp: Add <tuple> for std::tie, since r207593 removed ↵NAKAMURA Takumi2014-04-301-0/+1
| | | | | | FileSystem.h, it includes <tuple>. llvm-svn: 207614
* ARM: print COFF function header for Windows on ARMSaleem Abdulrasool2014-04-302-1/+68
| | | | | | | | | Emit the COFF header when printing out the function. This is important as the header contains two important pieces of information: the storage class for the symbol and the symbol type information. This bit of information is required for the linker to correctly identify the type of symbol that it is dealing with. llvm-svn: 207613
* [C++11] Use 'nullptr' in tablegen output files.Craig Topper2014-04-303-11/+11
| | | | llvm-svn: 207611
* De-virtualize or remove some methods that have no overrides nor override ↵Craig Topper2014-04-307-27/+7
| | | | | | anything. In some cases remove all together if there are no callers either. llvm-svn: 207610
* ARM: move llvm_unreachable useSaleem Abdulrasool2014-04-301-1/+1
| | | | | | | | When building with -Werror=covered-switch-default (as on the buildbots), the build would fail since all cases are covered by the switch. Move the llvm_unreachable to the end of the function as an annotation. llvm-svn: 207609
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