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* R600: Workaround for cayman loop bugVincent Lejeune2013-12-023-0/+46
| | | | llvm-svn: 196121
* Move getSymbolWithGlobalValueBase to TargetLoweringObjectFile.Rafael Espindola2013-12-028-27/+27
| | | | | | This allows it to be used in TargetLoweringObjectFileImpl.cpp. llvm-svn: 196117
* Introduce poor man's consumeToken() in X86AsmParserAlp Toker2013-12-021-18/+13
| | | | | | | | This makes the code a little more idiomatic. No change in behaviour. llvm-svn: 196113
* Remove dead code.Rafael Espindola2013-12-028-83/+0
| | | | | | | | | MO_JumpTableIndex and MO_ExternalSymbol don't show up on inline asm. Keeping parts of the old asm printer just to print inline asm to a string that we then parse back looks like a hack. llvm-svn: 196111
* Add tests for profile sample file parsing.Diego Novillo2013-12-026-0/+45
| | | | | | | The profile file parser needed some tests for its parsing actions. This adds tests for each of the error messages emitted by the parser. llvm-svn: 196106
* Output .eh_frames on COFF too now that the integrated as is used on mingw.Rafael Espindola2013-12-022-0/+15
| | | | llvm-svn: 196104
* ARM: decide whether to use movw/movt based on "minsize" attribute.Tim Northover2013-12-029-14/+49
| | | | llvm-svn: 196102
* Cut the gold plugin README down to sizeAlp Toker2013-12-021-14/+6
| | | | | | | This file hasn't been updated in years. Remove old information and point to the current documentation at GoldPlugin.rst. llvm-svn: 196100
* Fix dominator descendants for unreachable blocks.Diego Novillo2013-12-022-1/+30
| | | | | | | | | | | | | When a block is unreachable, asking its dom tree descendants should return the empty set. However, the computation of the descendants was causing a segmentation fault because the dom tree node we get from the basic block is initially NULL. Fixed by adding a test for a valid dom tree node before we iterate. The patch also adds some unit tests to the existing dom tree tests. llvm-svn: 196099
* [PM] [cleanup] Rearrange the public and private sections of this classChandler Carruth2013-12-021-19/+38
| | | | | | | | | | | | to be a bit more sensible. The public interface now is first followed by the implementation details. This also resolves a FIXME to make something private -- it was already possible as the one special caller was already a friend. No functionality changed. llvm-svn: 196095
* XCoreFrameLowering.cpp: Use [in,out] instead of [in] [out]. [-Wdocumentation]NAKAMURA Takumi2013-12-021-2/+2
| | | | llvm-svn: 196094
* [CMake] add_lit_target: Tests should be excluded from "Build Solution".NAKAMURA Takumi2013-12-021-0/+3
| | | | llvm-svn: 196093
* XCore target: Make handling of large frames not dependent upon an FP.Robert Lytton2013-12-029-216/+409
| | | | | | | | | | | | eliminateFrameIndex() has been reworked to handle both small & large frames with either a FP or SP. An additional Slot is required for Scavenging spills when not using FP for large frames. Reworked the handling of Register Scavenging. Whether we are using an FP or not, whether it is a large frame or not, and whether we are using a large code model or not are now independent. llvm-svn: 196091
* ARM: add pseudo-instructions for lit-pool global materialisationTim Northover2013-12-029-81/+179
| | | | | | | | | | | | These are used by MachO only at the moment, and (much like the existing MOVW/MOVT set) work around the fact that the labels used in the actual instructions often contain PC-dependent components, which means that repeatedly materialising the same global can't be CSEed. With small modifications, it could be adapted to how ELF finds the address of _GLOBAL_OFFSET_TABLE_, which would give similar benefits in PIC mode there. llvm-svn: 196090
* XCore: Unbreak C++11 build.Benjamin Kramer2013-12-021-3/+3
| | | | llvm-svn: 196089
* XCore target: fix large code model 'select' indirect address handling.Robert Lytton2013-12-022-6/+36
| | | | llvm-svn: 196088
* XCore target: Add large code modelRobert Lytton2013-12-026-29/+239
| | | | | | | | | | | | | | | | When using large code model: Global objects larger than 'CodeModelLargeSize' bytes are placed in sections named with a trailing ".large" The folded global address of such objects are lowered into the const pool. During inspection it was noted that LowerConstantPool() was using a default offset of zero. A fix was made, but due to only offsets of zero being generated, testing only verifies the change is not detrimental. Correct the flags emitted for explicitly specified sections. We assume the size of the object queried by getSectionForConstant() is never greater than CodeModelLargeSize. To handle greater than CodeModelLargeSize, changes to AsmPrinter would be required. llvm-svn: 196087
* XCore target: extend tests in preparationRobert Lytton2013-12-021-0/+66
| | | | llvm-svn: 196086
* XCore target: Fix eliminateFrameIndex() to handle large framesRobert Lytton2013-12-022-7/+60
| | | | | | | | Large frame offsets are loaded from the ConstantPool. Where possible, offsets are encoded using the smaller MKMSK instruction. Large frame offsets can only be used when there is a frame-pointer. llvm-svn: 196085
* XCore target: Enable frames larger than 65535 to be loweredRobert Lytton2013-12-022-138/+302
| | | | llvm-svn: 196084
* [tsan] fix instrumentation of vector vptr updates ↵Kostya Serebryany2013-12-022-4/+24
| | | | | | (https://code.google.com/p/thread-sanitizer/issues/detail?id=43) llvm-svn: 196079
* Update the LTO GoldPlugin documentationAlp Toker2013-12-021-17/+11
| | | | | | | | | * Update build instructions to reflect the current source tree layout. * Don't inflict CVS on readers; there's a perfectly good git mirror. * configure with --disable-werror making it possible to build using clang. * ar and nm-new now support the -plugin option. llvm-svn: 196069
* Remove leftovers from a non-MC asm printer.Rafael Espindola2013-12-022-168/+0
| | | | llvm-svn: 196068
* Remove #if 0 declarations.Rafael Espindola2013-12-021-8/+0
| | | | llvm-svn: 196067
* Remove dead code.Rafael Espindola2013-12-024-43/+2
| | | | llvm-svn: 196066
* Change the default of AsmWriterClassName and isMCAsmWriter.Rafael Espindola2013-12-0213-88/+10
| | | | llvm-svn: 196065
* Rename test with misspelt filenameAlp Toker2013-12-021-1/+1
| | | | llvm-svn: 196064
* Remove dead declarations.Rafael Espindola2013-12-022-8/+0
| | | | llvm-svn: 196063
* Refactor for clarity and efficiency.Rafael Espindola2013-12-021-23/+22
| | | | | | | The PPC GetSymbolFromOperand already prefixed stubs of MO_ExternalSymbol, so this should be a nop. llvm-svn: 196059
* Also test the created stubs on 32 bits.Rafael Espindola2013-12-011-0/+5
| | | | llvm-svn: 196052
* Add -mcpu to stackmap.llAndrew Trick2013-12-011-1/+1
| | | | llvm-svn: 196051
* ARM: fix bug in -Oz stack adjustment foldingTim Northover2013-12-015-23/+28
| | | | | | | | | | | Previously, we clobbered callee-saved registers when folding an "add sp, #N" into a "pop {rD, ...}" instruction. This change checks whether a register we're going to add to the "pop" could actually be live outside the function before doing so and should fix the issue. This should fix PR18081. llvm-svn: 196046
* Revamp error checking in the ms inline asm parser.Benjamin Kramer2013-12-011-46/+47
| | | | | | | | | - Actually abort when an error occurred. - Check that the frontend lookup worked when parsing length/size/type operators. Tested by a clang test. PR18096. llvm-svn: 196044
* Ensure bitcode encoding of linkage types stays stable. Patch by Boaz OurielMichael Kuperstein2013-12-012-0/+128
| | | | llvm-svn: 196042
* Use accessor methods instead.Bill Wendling2013-12-011-2/+1
| | | | llvm-svn: 196006
* Use 'unsigned char' to get this past gcc error message:Bill Wendling2013-12-011-3/+4
| | | | | | error: invalid conversion from 'unsigned char' to '{anonymous}::Sequence' llvm-svn: 196004
* Add a scheduling model (with itinerary) for the PPC POWER7Hal Finkel2013-11-304-2/+390
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a scheduling model for the POWER7 (P7) core, and enables the machine-instruction scheduler when targeting the P7. Scheduling for the P7, like earlier ooo PPC cores, requires considering both dispatch group hazards, and functional unit resources and latencies. These are both modeled in a combined itinerary. Dispatch group formation is still handled by the post-RA scheduler (which still needs to be updated for the P7, but nevertheless does a pretty good job). One interesting aspect of this change is that I've also enabled to use of AA duing CodeGen for the P7 (just as it is for the embedded cores). The benchmark results seem to support this decision (see below), and while this is normally useful for in-order cores, and not for ooo cores like the P7, I think that the dispatch slot hazards are enough like in-order resources to make the AA useful. Test suite significant performance differences (where negative is a speedup, and positive is a regression) vs. the current situation: MultiSource/Benchmarks/BitBench/drop3/drop3 with AA: N/A without AA: -28.7614% +/- 19.8356% (significantly against AA) MultiSource/Benchmarks/FreeBench/neural/neural with AA: -17.7406% +/- 11.2712% without AA: N/A (significantly in favor of AA) MultiSource/Benchmarks/SciMark2-C/scimark2 with AA: -11.2079% +/- 1.80543% without AA: -11.3263% +/- 2.79651% MultiSource/Benchmarks/TSVC/Symbolics-flt/Symbolics-flt with AA: -41.8649% +/- 17.0053% without AA: -34.5256% +/- 23.7072% MultiSource/Benchmarks/mafft/pairlocalalign with AA: 25.3016% +/- 17.8614% without AA: 38.6629% +/- 14.9391% (significantly in favor of AA) MultiSource/Benchmarks/sim/sim with AA: N/A without AA: 13.4844% +/- 7.18195% (significantly in favor of AA) SingleSource/Benchmarks/BenchmarkGame/Large/fasta with AA: 15.0664% +/- 6.70216% without AA: 12.7747% +/- 8.43043% SingleSource/Benchmarks/BenchmarkGame/puzzle with AA: 82.2713% +/- 26.3567% without AA: 75.7525% +/- 41.1842% SingleSource/Benchmarks/Misc/flops-2 with AA: -37.1621% +/- 20.7964% without AA: -35.2342% +/- 20.2999% (significantly in favor of AA) These are 99.5% confidence intervals from 5 runs per configuration. Regarding the choice to turn on AA during CodeGen, of these results, four seem significantly in favor of using AA, and one seems significantly against. I'm not making this decision based on these numbers alone, but these results seem consistent with results I have from other tests, and so I think that, on balance, using AA is a win. llvm-svn: 195981
* Split some PPC itinerary classesHal Finkel2013-11-3011-31/+154
| | | | | | | | | | | | | In preparation for adding scheduling definitions for the POWER7, split some PPC itinerary classes so that the P7's latencies and hazards can be better described. For the most part, this means differentiating indexed from non-index pre-increment loads and stores. Also, differentiate single from double-precision sqrt. No functionality change intended (except for a more-specific latency for single-precision sqrt on the A2). llvm-svn: 195980
* Convert a PPC test from grep to FileCheckHal Finkel2013-11-301-8/+27
| | | | | | | | Convert this test to FileCheck, and improve it to check for the instructions it is trying to exclude instead of checking for register use (especially because grepping for r1 can be thrown off, for example, by a use of r12). llvm-svn: 195979
* Desensitize a couple of PPC regression testsHal Finkel2013-11-302-6/+6
| | | | | | | Use CHECK-DAG to make these regression tests more resilient against changes in instruction scheduling. llvm-svn: 195978
* Update the cpu specified on some PPC regression testsHal Finkel2013-11-3011-12/+12
| | | | | | | | | | | Some of these tests did not specify a cpu but were also sensitive to instruction scheduling and/or register assignment choices. A few others similarly-sensitive tests specified a cpu (often the POWER7), and while the P7 currently uses the default model for PPC64, this will soon change. For those tests which should not really be cpu-dependent anyway, the cpu is set to the generic 'ppc64'. llvm-svn: 195977
* Test case for issue with microMIPS long branch.Zoran Jovanovic2013-11-301-0/+16437
| | | | llvm-svn: 195976
* Fixed issue with microMIPS long branch.Zoran Jovanovic2013-11-301-1/+3
| | | | llvm-svn: 195975
* [mips][msa] MSA loads and stores have a 10-bit offset. Account for this when ↵Daniel Sanders2013-11-302-5/+132
| | | | | | | | | lowering FrameIndex. This prevents the compiler from emitting invalid ld.[bhwd]'s and st.[bhwd]'s when the stack frame is between 512 and 32,768 bytes in size. llvm-svn: 195973
* [mips][msa] A small refactor to reduce patch noise in my next commitDaniel Sanders2013-11-301-15/+17
| | | | | | No functional change. An if-statement has been split into two nested if-statements. llvm-svn: 195972
* Force CPU type to unbreak unit tests on Haswell machines.Juergen Ributzka2013-11-305-5/+5
| | | | llvm-svn: 195971
* Reverse the order of eviction checks for possible compile time savings. No ↵Andrew Trick2013-11-291-3/+3
| | | | | | functionality. llvm-svn: 195969
* Part 1 of 3 patches that completes very long conditional branchesReed Kotler2013-11-293-16/+103
| | | | | | | | | | | | in constant islands for Mips16. We introdcuce JalB16 as a synomnym for Jal16. It makes it easier to read and is also necessary because Jal16 is a call instruction but JalB16 is being used as a branch. Various parts of LLVM will not work properly even in this late stage of the backend if we use what was declared as a call instruction to function as a branch. For one, basic block labels may not get emitted in some situations. llvm-svn: 195968
* Revert revision 195965.Zoran Jovanovic2013-11-292-16440/+1
| | | | llvm-svn: 195967
* mips: XFAIL llvm-cov testPetar Jovanovic2013-11-291-1/+1
| | | | | | | XFAIL llvm-cov.test for MIPS until big-endian issues are fixed for llvm-cov. The test does pass on MIPS little-endian. llvm-svn: 195966
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